596 lines
12 KiB
C
596 lines
12 KiB
C
/*
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* Copyright (C) 2012 BLX Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/initval.h>
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#include "gsc3280-i2s.h"
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#include "gsc3280-pcm.h"
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struct gsc3280_i2s {
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struct resource *mem;
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void __iomem *base;
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dma_addr_t phys_base;
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struct clk *clk_aic;
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struct clk *clk_i2s;
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struct gsc3280_pcm_config pcm_config_playback;
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struct gsc3280_pcm_config pcm_config_capture;
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};
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static inline uint32_t gsc3280_i2s_read(const struct gsc3280_i2s *i2s,
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unsigned int reg)
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{
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return readl(i2s->base + reg);
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}
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static inline void gsc3280_i2s_write(const struct gsc3280_i2s *i2s,
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uint32_t value, unsigned int reg)
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{
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writel(value, i2s->base + reg);
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}
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static int gsc3280_i2s_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct gsc3280_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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if (dai->active)
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return 0;
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/* reset_tx_fifos */
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gsc3280_i2s_write(i2s, 0x1,TXFFR);
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/* reset_rx_fifos */
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gsc3280_i2s_write(i2s, 0x1,RXFFR);
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/* flush_channel_rx_fifo */
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gsc3280_i2s_write(i2s, 0x1,RFF0);
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/* flush_channel_tx_fifo */
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gsc3280_i2s_write(i2s, 0x1,TFF0);
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/* i2s_channel_rx_disable */
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gsc3280_i2s_write(i2s, 0, RER0);
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/* i2s_channel_tx_disable */
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gsc3280_i2s_write(i2s, 0, TER0);
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/* i2s_channel_tx_enable */
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gsc3280_i2s_write(i2s, 1, TER0);
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/* i2s_channel_rx_enable */
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gsc3280_i2s_write(i2s, 1, RER0);
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/* enable_trans_block */
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gsc3280_i2s_write(i2s, 1, ITER);
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/* enable_i2s_clock */ /*slave or master */
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gsc3280_i2s_write(i2s, 1, CER);
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gsc3280_i2s_write(i2s, 0, IMR0);
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gsc3280_i2s_write(i2s, 2|1, DCTRL);
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gsc3280_i2s_write(i2s, 1, 0x1cc); //enable dma
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gsc3280_i2s_write(i2s, 1, 0x1c4); //enable dma
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gsc3280_i2s_write(i2s, 4, TFCR0);
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gsc3280_i2s_write(i2s, 4, RFCR0);
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#if 0
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//gsc3280_i2s_write(i2s, 1, ITER);
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//enable_trans_block
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//gsc3280_i2s_write(i2s, 1, TER0);
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//i2s_channel_tx_enable
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#endif
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return 0;
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}
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static void gsc3280_i2s_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct gsc3280_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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/* disable_trans_block */
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gsc3280_i2s_write(i2s, 0, ITER);
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/* disable_recev_block */
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gsc3280_i2s_write(i2s, 0, IRER);
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/* i2s_channel_rx_disable */
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gsc3280_i2s_write(i2s, 0, RER0);
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/* i2s_channel_tx_disable */
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gsc3280_i2s_write(i2s, 0, TER0);
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/* disable_i2s_clock */ /*slave or master */
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gsc3280_i2s_write(i2s, 0, CER);
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/* disable_i2s */
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gsc3280_i2s_write(i2s, 0, IER);
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}
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static int gsc3280_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct gsc3280_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
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gsc3280_i2s_write(i2s, 1, IER);
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gsc3280_i2s_write(i2s, 1, ITER);
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/* enable_trans_block */
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gsc3280_i2s_write(i2s, 1, TER0);
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#if 0
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gsc3280_i2s_write(i2s, 2, 0x200);
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gsc3280_i2s_write(i2s, 1, 0x1cc);
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#endif
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}else{
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gsc3280_i2s_write(i2s, 1, IER);
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/*enable_recev_block */
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gsc3280_i2s_write(i2s, 1, IRER);
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gsc3280_i2s_write(i2s, 1, RER0);
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#if 0
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gsc3280_i2s_write(i2s, 1|2, 0x200);
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gsc3280_i2s_write(i2s, 1, 0x1c4);
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#endif
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}
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
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gsc3280_i2s_write(i2s, 0, IER);
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/* disable_trans_block */
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gsc3280_i2s_write(i2s, 0, ITER);
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/* i2s_channel_tx_disable */
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gsc3280_i2s_write(i2s, 0, TER0);
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}else{
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gsc3280_i2s_write(i2s, 0, IER);
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/* disable_recev_block */
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gsc3280_i2s_write(i2s, 0, IRER);
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/* i2s_channel_rx_disable */
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gsc3280_i2s_write(i2s, 0, RER0);
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}
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int i2s_set_sample_cycle(struct gsc3280_i2s *i2s, int size)
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{
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int value;
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switch(size){
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case 16:
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value = gsc3280_i2s_read(i2s, CCR);
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value = (value & ~0x18) | CCR_CLK_16;
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gsc3280_i2s_write(i2s, value, CCR);
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break;
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case 24:
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value = gsc3280_i2s_read(i2s, CCR);
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value = (value & ~0x18) | CCR_CLK_24;
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gsc3280_i2s_write(i2s, value, CCR);
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break;
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case 32:
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value = gsc3280_i2s_read(i2s, CCR);
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value = (value & ~0x18) | CCR_CLK_32;
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gsc3280_i2s_write(i2s, value, CCR);
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break;
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default:
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printk(KERN_ERR"i2s can't support %d size data cycle!", size);
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return -1;
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}
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return 0;
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}
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static int i2s_set_rx_format(struct gsc3280_i2s *i2s, int format)
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{
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int regvalue;
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switch(format){
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case 0:
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regvalue = WLEN_0;
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break;
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case 12:
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regvalue = WLEN_12;
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break;
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case 16:
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regvalue = WLEN_16;
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break;
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case 20:
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regvalue = WLEN_20;
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break;
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case 24:
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regvalue = WLEN_24;
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break;
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case 32:
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regvalue = WLEN_32;
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break;
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default:
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printk(KERN_ERR"i2s can't support this format %d\n", format);
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return -1;
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}
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gsc3280_i2s_write(i2s, regvalue, RCR0);
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return 0;
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}
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static int i2s_set_tx_format(struct gsc3280_i2s *i2s, int format)
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{
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int regvalue;
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switch(format){
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case 0:
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regvalue = WLEN_0;
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break;
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case 12:
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regvalue = WLEN_12;
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break;
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case 16:
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regvalue = WLEN_16;
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break;
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case 20:
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regvalue = WLEN_20;
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break;
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case 24:
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regvalue = WLEN_24;
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break;
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case 32:
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regvalue = WLEN_32;
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break;
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default:
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printk(KERN_ERR"i2s can't support this format %d\n", format);
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return -1;
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}
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gsc3280_i2s_write(i2s, regvalue, TCR0);
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return 0;
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}
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static int gsc3280_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct gsc3280_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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i2s_set_sample_cycle(i2s, DATA_CYCLE_16);
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i2s_set_tx_format(i2s, DATA_FORMAT_16);
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i2s_set_rx_format(i2s, DATA_FORMAT_16);
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return 0;
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}
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static int gsc3280_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
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{
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struct gsc3280_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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//enum gsc3280_dma_width dma_width;
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int dma_width;
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struct gsc3280_pcm_config *pcm_config;
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unsigned int sample_size;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S8:
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case SNDRV_PCM_FORMAT_U8:
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sample_size = 0;
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//dma_width = DMA_WIDTH_8BIT;
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dma_width = 8;
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break;
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case SNDRV_PCM_FORMAT_S16:
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case SNDRV_PCM_FORMAT_U16:
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sample_size = 1;
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//dma_width = DMA_WIDTH_16BIT;
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dma_width = 16;
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break;
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default:
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return -EINVAL;
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}
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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pcm_config = &i2s->pcm_config_playback;
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#if 0
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pcm_config->dma_config.dst_width = dma_width;
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#endif
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} else {
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pcm_config = &i2s->pcm_config_capture;
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#if 0
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pcm_config->dma_config.src_width = dma_width;
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#endif
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}
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snd_soc_dai_set_dma_data(dai, substream, pcm_config);
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return 0;
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}
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static int gsc3280_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
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unsigned int freq, int dir)
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{
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int ret = 0;
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return ret;
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}
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static int gsc3280_i2s_suspend(struct snd_soc_dai *dai)
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{
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struct gsc3280_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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if (dai->active) {
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/* disable_trans_bloca */
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gsc3280_i2s_write(i2s, 0, ITER);
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/* disable_recev_block */
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gsc3280_i2s_write(i2s, 0, IRER);
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/* i2s_channel_rx_disable */
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gsc3280_i2s_write(i2s, 0, RER0);
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/* i2s_channel_tx_disable */
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gsc3280_i2s_write(i2s, 0, TER0);
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/* disable_i2s_clock */ /*slave or master */
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gsc3280_i2s_write(i2s, 0, CER);
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/* disable_i2s */
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gsc3280_i2s_write(i2s, 0, IER);
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}
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return 0;
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}
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static int gsc3280_i2s_resume(struct snd_soc_dai *dai)
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{
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struct gsc3280_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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if (dai->active) {
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/* enable_i2s */
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gsc3280_i2s_write(i2s, 1, IER);
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/* enable_trans_block */
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gsc3280_i2s_write(i2s, 1, ITER);
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/* enable_recev_block */
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gsc3280_i2s_write(i2s, 1, IRER);
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/* enable_i2s_clock */ /*slave or master */
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gsc3280_i2s_write(i2s, 1, CER);
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/* i2s_channel_rx_enable(0); */
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gsc3280_i2s_write(i2s, 1, RER0);
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/* i2s_channel_tx_enable(0); */
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gsc3280_i2s_write(i2s, 1, TER0);
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}
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return 0;
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}
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static void gsc3280_i2s_init_pcm_config(struct gsc3280_i2s *i2s)
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{
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i2s->pcm_config_playback.fifo_addr = i2s->phys_base + TXDMA;
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i2s->pcm_config_capture.fifo_addr = i2s->phys_base + RXDMA;
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}
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static int gsc3280_i2s_dai_probe(struct snd_soc_dai *dai)
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{
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/* uint32_t conf; */
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struct gsc3280_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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//writel(1,0xbc10aff0); //48K
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gsc3280_i2s_init_pcm_config(i2s);
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/* reset_tx_fifos */
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gsc3280_i2s_write(i2s, 0x1,TXFFR);
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/* reset_rx_fifos */
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gsc3280_i2s_write(i2s, 0x1,RXFFR);
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/* flush_channel_rx_fifo */
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gsc3280_i2s_write(i2s, 0x1,RFF0);
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/* flush_channel_tx_fifo */
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gsc3280_i2s_write(i2s, 0x1,TFF0);
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gsc3280_i2s_write(i2s, 6, RFCR0);
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/* set_channel_tx_fifo_depth */
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gsc3280_i2s_write(i2s, 2, TFCR0);
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/* i2s_channel_tx_disable(0); */
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gsc3280_i2s_write(i2s, 0, TER0);
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/* i2s_channel_rx_disable(0); */
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gsc3280_i2s_write(i2s, 0, RER0);
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return 0;
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}
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static int gsc3280_i2s_dai_remove(struct snd_soc_dai *dai)
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{
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#if 0
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struct gsc3280_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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clk_disable(i2s->clk_aic);
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#endif
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return 0;
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}
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static struct snd_soc_dai_ops gsc3280_i2s_dai_ops = {
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.startup = gsc3280_i2s_startup,
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.shutdown = gsc3280_i2s_shutdown,
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.trigger = gsc3280_i2s_trigger,
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.hw_params = gsc3280_i2s_hw_params,
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.set_fmt = gsc3280_i2s_set_fmt,
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.set_sysclk = gsc3280_i2s_set_sysclk,
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};
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#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_S16_LE)
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static struct snd_soc_dai_driver gsc3280_i2s_dai = {
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.probe = gsc3280_i2s_dai_probe,
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.remove = gsc3280_i2s_dai_remove,
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.playback = {
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = JZ4740_I2S_FMTS,
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},
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.capture = {
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = JZ4740_I2S_FMTS,
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},
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.symmetric_rates = 1,
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.ops = &gsc3280_i2s_dai_ops,
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.suspend = gsc3280_i2s_suspend,
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.resume = gsc3280_i2s_resume,
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};
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static int __devinit gsc3280_i2s_dev_probe(struct platform_device *pdev)
|
|
{
|
|
struct gsc3280_i2s *i2s;
|
|
int ret;
|
|
|
|
i2s = kzalloc(sizeof(*i2s), GFP_KERNEL);
|
|
|
|
if (!i2s)
|
|
return -ENOMEM;
|
|
|
|
i2s->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!i2s->mem) {
|
|
ret = -ENOENT;
|
|
goto err_free;
|
|
}
|
|
|
|
i2s->mem = request_mem_region(i2s->mem->start, resource_size(i2s->mem),
|
|
pdev->name);
|
|
if (!i2s->mem) {
|
|
ret = -EBUSY;
|
|
goto err_free;
|
|
}
|
|
|
|
i2s->base = ioremap_nocache(i2s->mem->start, resource_size(i2s->mem));
|
|
if (!i2s->base) {
|
|
ret = -EBUSY;
|
|
goto err_release_mem_region;
|
|
}
|
|
|
|
i2s->phys_base = i2s->mem->start;
|
|
|
|
i2s->clk_i2s = clk_get(&pdev->dev, "i2s");
|
|
if(!i2s->clk_i2s){
|
|
ret = -ENODEV;
|
|
goto err_release_mem_region;
|
|
}
|
|
clk_enable(i2s->clk_i2s);
|
|
|
|
platform_set_drvdata(pdev, i2s);
|
|
ret = snd_soc_register_dai(&pdev->dev, &gsc3280_i2s_dai);
|
|
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register DAI\n");
|
|
goto err_clk_put_i2s;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_clk_put_i2s:
|
|
clk_put(i2s->clk_i2s);
|
|
err_release_mem_region:
|
|
release_mem_region(i2s->mem->start, resource_size(i2s->mem));
|
|
err_free:
|
|
iounmap(i2s->base);
|
|
kfree(i2s);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __devexit gsc3280_i2s_dev_remove(struct platform_device *pdev)
|
|
{
|
|
struct gsc3280_i2s *i2s = platform_get_drvdata(pdev);
|
|
|
|
snd_soc_unregister_dai(&pdev->dev);
|
|
|
|
#if 0
|
|
clk_put(i2s->clk_i2s);
|
|
clk_put(i2s->clk_aic);
|
|
#endif
|
|
|
|
iounmap(i2s->base);
|
|
release_mem_region(i2s->mem->start, resource_size(i2s->mem));
|
|
platform_set_drvdata(pdev, NULL);
|
|
kfree(i2s);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver gsc3280_i2s_driver = {
|
|
.probe = gsc3280_i2s_dev_probe,
|
|
.remove = __devexit_p(gsc3280_i2s_dev_remove),
|
|
.driver = {
|
|
.name = "gsc3280-i2s",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init gsc3280_i2s_init(void)
|
|
{
|
|
return platform_driver_register(&gsc3280_i2s_driver);
|
|
}
|
|
module_init(gsc3280_i2s_init);
|
|
|
|
static void __exit gsc3280_i2s_exit(void)
|
|
{
|
|
platform_driver_unregister(&gsc3280_i2s_driver);
|
|
}
|
|
module_exit(gsc3280_i2s_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:gsc3280-i2s");
|