237 lines
6.5 KiB
C
237 lines
6.5 KiB
C
#include <linux/io.h>
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#include "common.h"
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#include "gsc3280mac_dma.h"
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#undef GSC3280MAC_DMA_DEBUG
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#ifdef GSC3280MAC_DMA_DEBUG
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#define GSC3280MAC_LIB_DBG(fmt, args...) printk(fmt, ## args)
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#else
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#define GSC3280MAC_LIB_DBG(fmt, args...) do { } while (0)
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#endif
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/* CSR1 enables the transmit DMA to check for new descriptor */
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void gsc3280mac_enable_dma_transmission(void __iomem *ioaddr)
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{
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writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
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}
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void gsc3280mac_enable_dma_irq(void __iomem *ioaddr)
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{
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writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
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}
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void gsc3280mac_disable_dma_irq(void __iomem *ioaddr)
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{
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writel(0, ioaddr + DMA_INTR_ENA);
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}
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void gsc3280mac_dma_start_tx(void __iomem *ioaddr)
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{
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u32 value = readl(ioaddr + DMA_CONTROL);
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value |= DMA_CONTROL_ST;
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writel(value, ioaddr + DMA_CONTROL);
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}
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void gsc3280mac_dma_stop_tx(void __iomem *ioaddr)
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{
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u32 value = readl(ioaddr + DMA_CONTROL);
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value &= ~DMA_CONTROL_ST;
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writel(value, ioaddr + DMA_CONTROL);
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}
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void gsc3280mac_dma_start_rx(void __iomem *ioaddr)
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{
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u32 value = readl(ioaddr + DMA_CONTROL);
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value |= DMA_CONTROL_SR;
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writel(value, ioaddr + DMA_CONTROL);
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}
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void gsc3280mac_dma_stop_rx(void __iomem *ioaddr)
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{
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u32 value = readl(ioaddr + DMA_CONTROL);
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value &= ~DMA_CONTROL_SR;
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writel(value, ioaddr + DMA_CONTROL);
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}
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#ifdef GSC3280MAC_DMA_DEBUG
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static void show_tx_process_state(unsigned int status)
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{
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unsigned int state;
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state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
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switch (state) {
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case 0:
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pr_info("- TX (Stopped): Reset or Stop command\n");
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break;
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case 1:
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pr_info("- TX (Running):Fetching the Tx desc\n");
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break;
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case 2:
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pr_info("- TX (Running): Waiting for end of tx\n");
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break;
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case 3:
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pr_info("- TX (Running): Reading the data "
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"and queuing the data into the Tx buf\n");
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break;
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case 6:
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pr_info("- TX (Suspended): Tx Buff Underflow "
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"or an unavailable Transmit descriptor\n");
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break;
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case 7:
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pr_info("- TX (Running): Closing Tx descriptor\n");
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break;
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default:
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break;
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}
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}
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static void show_rx_process_state(unsigned int status)
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{
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unsigned int state;
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state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
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switch (state) {
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case 0:
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pr_info("- RX (Stopped): Reset or Stop command\n");
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break;
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case 1:
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pr_info("- RX (Running): Fetching the Rx desc\n");
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break;
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case 2:
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pr_info("- RX (Running):Checking for end of pkt\n");
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break;
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case 3:
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pr_info("- RX (Running): Waiting for Rx pkt\n");
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break;
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case 4:
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pr_info("- RX (Suspended): Unavailable Rx buf\n");
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break;
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case 5:
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pr_info("- RX (Running): Closing Rx descriptor\n");
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break;
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case 6:
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pr_info("- RX(Running): Flushing the current frame"
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" from the Rx buf\n");
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break;
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case 7:
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pr_info("- RX (Running): Queuing the Rx frame"
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" from the Rx buf into memory\n");
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break;
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default:
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break;
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}
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}
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#endif
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int gsc3280mac_dma_interrupt(void __iomem *ioaddr,
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struct gsc3280mac_extra_stats *x)
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{
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int ret = 0;
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/* read the status register (CSR5) */
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u32 intr_status = readl(ioaddr + DMA_STATUS);
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GSC3280MAC_LIB_DBG(KERN_INFO "%s: [CSR5: 0x%08x]\n", __func__, intr_status);
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#ifdef GSC3280MAC_DMA_DEBUG
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/* It displays the DMA process states (CSR5 register) */
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show_tx_process_state(intr_status);
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show_rx_process_state(intr_status);
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#endif
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/* ABNORMAL interrupts */
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if (unlikely(intr_status & DMA_STATUS_AIS)) {
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GSC3280MAC_LIB_DBG(KERN_INFO "CSR5[15] DMA ABNORMAL IRQ: ");
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if (unlikely(intr_status & DMA_STATUS_UNF)) {
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GSC3280MAC_LIB_DBG(KERN_INFO "transmit underflow\n");
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ret = tx_hard_error_bump_tc;
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x->tx_undeflow_irq++;
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}
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if (unlikely(intr_status & DMA_STATUS_TJT)) {
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GSC3280MAC_LIB_DBG(KERN_INFO "transmit jabber\n");
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x->tx_jabber_irq++;
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}
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if (unlikely(intr_status & DMA_STATUS_OVF)) {
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GSC3280MAC_LIB_DBG(KERN_INFO "recv overflow\n");
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x->rx_overflow_irq++;
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}
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if (unlikely(intr_status & DMA_STATUS_RU)) {
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GSC3280MAC_LIB_DBG(KERN_INFO "receive buffer unavailable\n");
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x->rx_buf_unav_irq++;
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}
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if (unlikely(intr_status & DMA_STATUS_RPS)) {
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GSC3280MAC_LIB_DBG(KERN_INFO "receive process stopped\n");
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x->rx_process_stopped_irq++;
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}
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if (unlikely(intr_status & DMA_STATUS_RWT)) {
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GSC3280MAC_LIB_DBG(KERN_INFO "receive watchdog\n");
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x->rx_watchdog_irq++;
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}
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if (unlikely(intr_status & DMA_STATUS_ETI)) {
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GSC3280MAC_LIB_DBG(KERN_INFO "transmit early interrupt\n");
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x->tx_early_irq++;
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}
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if (unlikely(intr_status & DMA_STATUS_TPS)) {
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GSC3280MAC_LIB_DBG(KERN_INFO "transmit process stopped\n");
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x->tx_process_stopped_irq++;
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ret = tx_hard_error;
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}
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if (unlikely(intr_status & DMA_STATUS_FBI)) {
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GSC3280MAC_LIB_DBG(KERN_INFO "fatal bus error\n");
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x->fatal_bus_error_irq++;
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ret = tx_hard_error;
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}
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}
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/* TX/RX NORMAL interrupts */
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if (intr_status & DMA_STATUS_NIS) {
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x->normal_irq_n++;
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if (likely((intr_status & DMA_STATUS_RI) ||
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(intr_status & (DMA_STATUS_TI))))
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ret = handle_tx_rx;
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}
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/* Optional hardware blocks, interrupts should be disabled */
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if (unlikely(intr_status &
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(DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
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pr_info("%s: unexpected status %08x\n", __func__, intr_status);
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/* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
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writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
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GSC3280MAC_LIB_DBG(KERN_INFO "\n\n");
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return ret;
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}
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void gsc3280mac_dma_flush_tx_fifo(void __iomem *ioaddr)
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{
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u32 csr6 = readl(ioaddr + DMA_CONTROL);
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writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
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do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
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}
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void gsc3280mac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
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unsigned int high, unsigned int low)
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{
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unsigned long data;
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data = (addr[5] << 8) | addr[4];
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writel(data, ioaddr + high);
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data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
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writel(data, ioaddr + low);
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}
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void gsc3280mac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
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unsigned int high, unsigned int low)
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{
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unsigned int hi_addr, lo_addr;
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/* Read the MAC address from the hardware */
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hi_addr = readl(ioaddr + high);
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lo_addr = readl(ioaddr + low);
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/* Extract the MAC address from the high and low words */
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addr[0] = lo_addr & 0xff;
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addr[1] = (lo_addr >> 8) & 0xff;
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addr[2] = (lo_addr >> 16) & 0xff;
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addr[3] = (lo_addr >> 24) & 0xff;
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addr[4] = hi_addr & 0xff;
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addr[5] = (hi_addr >> 8) & 0xff;
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}
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