85 lines
4.3 KiB
C
85 lines
4.3 KiB
C
/* DMA CRS Control and Status Register Mapping */
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#define DMA_BUS_MODE 0x00001000 /* Bus Mode */
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#define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */
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#define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */
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#define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */
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#define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
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#define DMA_STATUS 0x00001014 /* Status Register */
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#define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */
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#define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */
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#define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */
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#define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */
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#define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */
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/* DMA Control register defines */
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#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
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#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
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/* DMA Normal interrupt */
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#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
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#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
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#define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */
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#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
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#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
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#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
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DMA_INTR_ENA_TIE)
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/* DMA Abnormal interrupt */
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#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
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#define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
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#define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
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#define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
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#define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
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#define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
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#define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
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#define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
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#define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
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#define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
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#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
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DMA_INTR_ENA_UNE)
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/* DMA default interrupt mask */
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#define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
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/* DMA Status register defines */
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#define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */
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#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
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#define DMA_STATUS_GLI 0x04000000 /* GSC3280MAC Line interface int */
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#define DMA_STATUS_GMI 0x08000000
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#define DMA_STATUS_GLI 0x04000000
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#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
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#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
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#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
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#define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
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#define DMA_STATUS_TS_SHIFT 20
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#define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
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#define DMA_STATUS_RS_SHIFT 17
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#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
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#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
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#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
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#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
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#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
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#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
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#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
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#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
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#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
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#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
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#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
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#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
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#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
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#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
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#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
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#define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */
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extern void gsc3280mac_enable_dma_transmission(void __iomem *ioaddr);
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extern void gsc3280mac_enable_dma_irq(void __iomem *ioaddr);
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extern void gsc3280mac_disable_dma_irq(void __iomem *ioaddr);
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extern void gsc3280mac_dma_start_tx(void __iomem *ioaddr);
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extern void gsc3280mac_dma_stop_tx(void __iomem *ioaddr);
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extern void gsc3280mac_dma_start_rx(void __iomem *ioaddr);
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extern void gsc3280mac_dma_stop_rx(void __iomem *ioaddr);
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extern int gsc3280mac_dma_interrupt(void __iomem *ioaddr,
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struct gsc3280mac_extra_stats *x);
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