130 lines
3.9 KiB
C
130 lines
3.9 KiB
C
#include "gsc3280mac1000.h"
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#include "gsc3280mac_dma.h"
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static int gsc3280mac1000_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx,
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u32 dma_rx)
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{
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u32 value = readl(ioaddr + DMA_BUS_MODE);
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int limit;
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/* DMA SW reset */
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value |= DMA_BUS_MODE_SFT_RESET;
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writel(value, ioaddr + DMA_BUS_MODE);
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limit = 15000;
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while (limit--) {
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if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
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break;
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}
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if (limit < 0)
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return -EBUSY;
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//value = /*DMA_BUS_MODE_FB |*/ DMA_BUS_MODE_4PBL |
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value = DMA_BUS_MODE_FB | DMA_BUS_MODE_4PBL |
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((pbl << DMA_BUS_MODE_PBL_SHIFT) |
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(pbl << DMA_BUS_MODE_RPBL_SHIFT));
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#ifdef CONFIG_GSC3280MAC_DA
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value |= DMA_BUS_MODE_DA; /* Rx has priority over tx */
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#endif
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writel(value, ioaddr + DMA_BUS_MODE);
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/* Mask interrupts by writing to CSR7 */
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writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
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/* The base address of the RX/TX descriptor lists must be written into
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* DMA CSR3 and CSR4, respectively. */
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writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
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writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
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return 0;
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}
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static void gsc3280mac1000_dma_operation_mode(void __iomem *ioaddr, int txmode,
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int rxmode)
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{
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u32 csr6 = readl(ioaddr + DMA_CONTROL);
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if (txmode == SF_DMA_MODE) {
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CHIP_DBG(KERN_DEBUG "GMAC: enable TX store and forward mode\n");
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/* Transmit COE type 2 cannot be done in cut-through mode. */
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csr6 |= DMA_CONTROL_TSF;
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/* Operating on second frame increase the performance
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* especially when transmit store-and-forward is used.*/
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csr6 |= DMA_CONTROL_OSF;
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} else {
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CHIP_DBG(KERN_DEBUG "GMAC: disabling TX store and forward mode"
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" (threshold = %d)\n", txmode);
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csr6 &= ~DMA_CONTROL_TSF;
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csr6 &= DMA_CONTROL_TC_TX_MASK;
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/* Set the transmit threshold */
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if (txmode <= 32)
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csr6 |= DMA_CONTROL_TTC_32;
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else if (txmode <= 64)
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csr6 |= DMA_CONTROL_TTC_64;
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else if (txmode <= 128)
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csr6 |= DMA_CONTROL_TTC_128;
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else if (txmode <= 192)
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csr6 |= DMA_CONTROL_TTC_192;
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else
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csr6 |= DMA_CONTROL_TTC_256;
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}
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if (rxmode == SF_DMA_MODE) {
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CHIP_DBG(KERN_DEBUG "GMAC: enable RX store and forward mode\n");
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csr6 |= DMA_CONTROL_RSF;
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// csr6 |= DMA_CONTROL_DT; //NOTE: set 1 to report IP/TCP/UDP/ICMP checksum error frame to CPU, set 0 to drop the frame silently.
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} else {
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CHIP_DBG(KERN_DEBUG "GMAC: disabling RX store and forward mode"
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" (threshold = %d)\n", rxmode);
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csr6 &= ~DMA_CONTROL_RSF;
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csr6 &= DMA_CONTROL_TC_RX_MASK;
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if (rxmode <= 32)
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csr6 |= DMA_CONTROL_RTC_32;
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else if (rxmode <= 64)
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csr6 |= DMA_CONTROL_RTC_64;
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else if (rxmode <= 96)
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csr6 |= DMA_CONTROL_RTC_96;
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else
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csr6 |= DMA_CONTROL_RTC_128;
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}
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writel(csr6, ioaddr + DMA_CONTROL);
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}
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/* Not yet implemented --- no RMON module */
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static void gsc3280mac1000_dma_diagnostic_fr(void *data,
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struct gsc3280mac_extra_stats *x, void __iomem *ioaddr)
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{
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return;
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}
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static void gsc3280mac1000_dump_dma_regs(void __iomem *ioaddr)
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{
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int i;
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pr_info(" DMA registers\n");
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for (i = 0; i < 22; i++) {
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if ((i < 9) || (i > 17)) {
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int offset = i * 4;
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pr_err("\t Reg No. %d (offset 0x%x): 0x%08x\n", i,
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(DMA_BUS_MODE + offset),
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readl(ioaddr + DMA_BUS_MODE + offset));
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}
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}
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}
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const struct gsc3280mac_dma_ops gsc3280mac1000_dma_ops = {
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.init = gsc3280mac1000_dma_init,
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.dump_regs = gsc3280mac1000_dump_dma_regs,
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.dma_mode = gsc3280mac1000_dma_operation_mode,
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.dma_diagnostic_fr = gsc3280mac1000_dma_diagnostic_fr,
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.enable_dma_transmission = gsc3280mac_enable_dma_transmission,
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.enable_dma_irq = gsc3280mac_enable_dma_irq,
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.disable_dma_irq = gsc3280mac_disable_dma_irq,
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.start_tx = gsc3280mac_dma_start_tx,
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.stop_tx = gsc3280mac_dma_stop_tx,
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.start_rx = gsc3280mac_dma_start_rx,
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.stop_rx = gsc3280mac_dma_stop_rx,
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.dma_interrupt = gsc3280mac_dma_interrupt,
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};
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