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ckfwq/linux-3.0.4/drivers/dma/gsc3280_dmac.c

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/*
* Driver for the GSC3280 DMA Controller
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "gsc3280_dmac.h"
#define GSC3280_DEFAULT_CTLLO(private) ({ \
struct gsc3280_dma_slave *__slave = (private); \
int dms = __slave ? __slave->dst_master : 0; \
int sms = __slave ? __slave->src_master : 1; \
u8 smsize = __slave ? __slave->src_msize : GSC3280_DMA_MSIZE_16; \
u8 dmsize = __slave ? __slave->dst_msize : GSC3280_DMA_MSIZE_16; \
\
(GSC3280_CTLL_DST_MSIZE(dmsize) \
| GSC3280_CTLL_SRC_MSIZE(smsize) \
| GSC3280_CTLL_LLP_D_EN \
| GSC3280_CTLL_LLP_S_EN \
| GSC3280_CTLL_DMS(dms) \
| GSC3280_CTLL_SMS(sms)); \
})
#define GSC3280_MAX_COUNT 4095U
#define NR_DESCS_PER_CHANNEL 64
static struct device *chan2dev(struct dma_chan *chan)
{
return &chan->dev->device;
}
static struct device *chan2parent(struct dma_chan *chan)
{
return chan->dev->device.parent;
}
static struct gsc3280_desc *gsc3280_first_active(struct gsc3280_dma_chan *gsc)
{
return list_entry(gsc->active_list.next, struct gsc3280_desc, desc_node);
}
static struct gsc3280_desc *gsc3280_desc_get(struct gsc3280_dma_chan *gsc)
{
struct gsc3280_desc *desc, *_desc;
struct gsc3280_desc *ret = NULL;
unsigned int i = 0;
unsigned long flags;
spin_lock_irqsave(&gsc->lock, flags);
list_for_each_entry_safe(desc, _desc, &gsc->free_list, desc_node) {
if (async_tx_test_ack(&desc->txd)) {
list_del(&desc->desc_node);
ret = desc;
break;
}
dev_dbg(chan2dev(&gsc->chan), "desc %p not ACKed\n", desc);
i++;
}
spin_unlock_irqrestore(&gsc->lock, flags);
dev_vdbg(chan2dev(&gsc->chan), "scanned %u descriptors on freelist\n", i);
return ret;
}
static void gsc3280_sync_desc_for_cpu(struct gsc3280_dma_chan *gsc, struct gsc3280_desc *desc)
{
struct gsc3280_desc *child;
list_for_each_entry(child, &desc->tx_list, desc_node)
dma_sync_single_for_cpu(chan2parent(&gsc->chan),
child->txd.phys, sizeof(child->lli),
DMA_TO_DEVICE);
dma_sync_single_for_cpu(chan2parent(&gsc->chan),
desc->txd.phys, sizeof(desc->lli),
DMA_TO_DEVICE);
}
/*
* Move a descriptor, including any children, to the free list.
* `desc' must not be on any lists.
*/
static void gsc3280_desc_put(struct gsc3280_dma_chan *gsc, struct gsc3280_desc *desc)
{
unsigned long flags;
if (desc) {
struct gsc3280_desc *child;
gsc3280_sync_desc_for_cpu(gsc, desc);
spin_lock_irqsave(&gsc->lock, flags);
list_for_each_entry(child, &desc->tx_list, desc_node)
dev_vdbg(chan2dev(&gsc->chan),
"moving child desc %p to freelist\n",
child);
list_splice_init(&desc->tx_list, &gsc->free_list);
dev_vdbg(chan2dev(&gsc->chan), "moving desc %p to freelist\n", desc);
list_add(&desc->desc_node, &gsc->free_list);
spin_unlock_irqrestore(&gsc->lock, flags);
}
}
/* Called with gsc->lock held and bh disabled */
static dma_cookie_t
gsc3280_assign_cookie(struct gsc3280_dma_chan *gsc, struct gsc3280_desc *desc)
{
dma_cookie_t cookie = gsc->chan.cookie;
if (++cookie < 0)
cookie = 1;
gsc->chan.cookie = cookie;
desc->txd.cookie = cookie;
return cookie;
}
/*----------------------------------------------------------------------*/
/* Called with gsc->lock held and bh disabled */
static void gsc3280_dostart(struct gsc3280_dma_chan *gsc, struct gsc3280_desc *first)
{
struct gsc3280_dma *gs = to_gsc3280_dma(gsc->chan.device);
/* ASSERT: channel is idle */
if (dma_readl(gs, CH_EN) & gsc->mask) {
dev_err(chan2dev(&gsc->chan),
"BUG: Attempted to start non-idle channel\n");
dev_err(chan2dev(&gsc->chan),
" SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
channel_readl(gsc, SAR),
channel_readl(gsc, DAR),
channel_readl(gsc, LLP),
channel_readl(gsc, CTL_HI),
channel_readl(gsc, CTL_LO));
/* The tasklet will hopefully advance the queue... */
return;
}
channel_writel(gsc, LLP, first->txd.phys);
channel_writel(gsc, CTL_LO,
GSC3280_CTLL_LLP_D_EN | GSC3280_CTLL_LLP_S_EN);
channel_writel(gsc, CTL_HI, 0);
channel_set_bit(gs, CH_EN, gsc->mask);
}
/*----------------------------------------------------------------------*/
static void
gsc3280_descriptor_complete(struct gsc3280_dma_chan *gsc, struct gsc3280_desc *desc,
bool callback_required)
{
dma_async_tx_callback callback = NULL;
void *param = NULL;
struct dma_async_tx_descriptor *txd = &desc->txd;
struct gsc3280_desc *child;
unsigned long flags;
dev_vdbg(chan2dev(&gsc->chan), "descriptor %u complete\n", txd->cookie);
spin_lock_irqsave(&gsc->lock, flags);
gsc->completed = txd->cookie;
if (callback_required) {
callback = txd->callback;
param = txd->callback_param;
}
gsc3280_sync_desc_for_cpu(gsc, desc);
/* async_tx_ack */
list_for_each_entry(child, &desc->tx_list, desc_node)
async_tx_ack(&child->txd);
async_tx_ack(&desc->txd);
list_splice_init(&desc->tx_list, &gsc->free_list);
list_move(&desc->desc_node, &gsc->free_list);
if (!gsc->chan.private) {
struct device *parent = chan2parent(&gsc->chan);
if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
dma_unmap_single(parent, desc->lli.dar,
desc->len, DMA_FROM_DEVICE);
else
dma_unmap_page(parent, desc->lli.dar,
desc->len, DMA_FROM_DEVICE);
}
if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
dma_unmap_single(parent, desc->lli.sar,
desc->len, DMA_TO_DEVICE);
else
dma_unmap_page(parent, desc->lli.sar,
desc->len, DMA_TO_DEVICE);
}
}
spin_unlock_irqrestore(&gsc->lock, flags);
if (callback_required && callback)
callback(param);
}
static void gsc3280_complete_all(struct gsc3280_dma *gs, struct gsc3280_dma_chan *gsc)
{
struct gsc3280_desc *desc, *_desc;
LIST_HEAD(list);
unsigned long flags;
spin_lock_irqsave(&gsc->lock, flags);
if (dma_readl(gs, CH_EN) & gsc->mask) {
dev_err(chan2dev(&gsc->chan),
"BUG: XFER bit set, but channel not idle!\n");
/* Try to continue after resetting the channel... */
channel_clear_bit(gs, CH_EN, gsc->mask);
while (dma_readl(gs, CH_EN) & gsc->mask)
cpu_relax();
}
/*
* Submit queued descriptors ASAP, i.e. before we go through
* the completed ones.
*/
list_splice_init(&gsc->active_list, &list);
if (!list_empty(&gsc->queue)) {
list_move(gsc->queue.next, &gsc->active_list);
gsc3280_dostart(gsc, gsc3280_first_active(gsc));
}
spin_unlock_irqrestore(&gsc->lock, flags);
list_for_each_entry_safe(desc, _desc, &list, desc_node)
gsc3280_descriptor_complete(gsc, desc, true);
}
static void gsc3280_scan_descriptors(struct gsc3280_dma *gs, struct gsc3280_dma_chan *gsc)
{
dma_addr_t llp;
struct gsc3280_desc *desc, *_desc;
struct gsc3280_desc *child;
u32 status_xfer;
unsigned long flags;
spin_lock_irqsave(&gsc->lock, flags);
/*
* Clear block interrupt flag before scanning so that we don't
* miss any, and read LLP before RAW_XFER to ensure it is
* valid if we decide to scan the list.
*/
dma_writel(gs, CLEAR.BLOCK, gsc->mask);
llp = channel_readl(gsc, LLP);
status_xfer = dma_readl(gs, RAW.XFER);
if (status_xfer & gsc->mask) {
/* Everything we've submitted is done */
dma_writel(gs, CLEAR.XFER, gsc->mask);
spin_unlock_irqrestore(&gsc->lock, flags);
gsc3280_complete_all(gs, gsc);
return;
}
if (list_empty(&gsc->active_list)) {
spin_unlock_irqrestore(&gsc->lock, flags);
return;
}
dev_vdbg(chan2dev(&gsc->chan), "scan_descriptors: llp=0x%x\n", llp);
list_for_each_entry_safe(desc, _desc, &gsc->active_list, desc_node) {
/* check first descriptors addr */
if (desc->txd.phys == llp) {
spin_unlock_irqrestore(&gsc->lock, flags);
return;
}
/* check first descriptors llp */
if (desc->lli.llp == llp) {
/* This one is currently in progress */
spin_unlock_irqrestore(&gsc->lock, flags);
return;
}
list_for_each_entry(child, &desc->tx_list, desc_node)
if (child->lli.llp == llp) {
/* Currently in progress */
spin_unlock_irqrestore(&gsc->lock, flags);
return;
}
/*
* No descriptors so far seem to be in progress, i.e.
* this one must be done.
*/
spin_unlock_irqrestore(&gsc->lock, flags);
gsc3280_descriptor_complete(gsc, desc, true);
spin_lock_irqsave(&gsc->lock, flags);
}
dev_err(chan2dev(&gsc->chan),
"BUG: All descriptors done, but channel not idle!\n");
/* Try to continue after resetting the channel... */
channel_clear_bit(gs, CH_EN, gsc->mask);
while (dma_readl(gs, CH_EN) & gsc->mask)
cpu_relax();
if (!list_empty(&gsc->queue)) {
list_move(gsc->queue.next, &gsc->active_list);
gsc3280_dostart(gsc, gsc3280_first_active(gsc));
}
spin_unlock_irqrestore(&gsc->lock, flags);
}
static void gsc3280_dump_lli(struct gsc3280_dma_chan *gsc, struct gsc3280_lli *lli)
{
dev_printk(KERN_CRIT, chan2dev(&gsc->chan),
" desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
lli->sar, lli->dar, lli->llp,
lli->ctlhi, lli->ctllo);
}
static void gsc3280_handle_error(struct gsc3280_dma *gs, struct gsc3280_dma_chan *gsc)
{
struct gsc3280_desc *bad_desc;
struct gsc3280_desc *child;
unsigned long flags;
gsc3280_scan_descriptors(gs, gsc);
spin_lock_irqsave(&gsc->lock, flags);
/*
* The descriptor currently at the head of the active list is
* borked. Since we don't have any way to report errors, we'll
* just have to scream loudly and try to carry on.
*/
bad_desc = gsc3280_first_active(gsc);
list_del_init(&bad_desc->desc_node);
list_move(gsc->queue.next, gsc->active_list.prev);
/* Clear the error flag and try to restart the controller */
dma_writel(gs, CLEAR.ERROR, gsc->mask);
if (!list_empty(&gsc->active_list))
gsc3280_dostart(gsc, gsc3280_first_active(gsc));
/*
* KERN_CRITICAL may seem harsh, but since this only happens
* when someone submits a bad physical address in a
* descriptor, we should consider ourselves lucky that the
* controller flagged an error instead of scribbling over
* random memory locations.
*/
dev_printk(KERN_CRIT, chan2dev(&gsc->chan),
"Bad descriptor submitted for DMA!\n");
dev_printk(KERN_CRIT, chan2dev(&gsc->chan),
" cookie: %d\n", bad_desc->txd.cookie);
gsc3280_dump_lli(gsc, &bad_desc->lli);
list_for_each_entry(child, &bad_desc->tx_list, desc_node)
gsc3280_dump_lli(gsc, &child->lli);
spin_unlock_irqrestore(&gsc->lock, flags);
/* Pretend the descriptor completed successfully */
gsc3280_descriptor_complete(gsc, bad_desc, true);
}
/* --------------------- Cyclic DMA API extensions -------------------- */
inline int gsc3280_dma_set_src_addr(struct dma_chan *chan, dma_addr_t src)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
channel_writel(gsc,SAR,src);
return 0;
}
EXPORT_SYMBOL(gsc3280_dma_set_src_addr);
inline int gsc3280_dma_set_dst_addr(struct dma_chan *chan, dma_addr_t dst)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
channel_writel(gsc,DAR,dst);
return 0;
}
EXPORT_SYMBOL(gsc3280_dma_set_dst_addr);
inline int gsc3280_dma_set_dma_count(struct dma_chan *chan, unsigned int count, enum dma_data_direction direction)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
struct gsc3280_dma_slave *gss = chan->private;
int reg_width = gss->reg_width;
int mem_width = gss->mem_width;
switch(direction){
case DMA_TO_DEVICE:
channel_writel(gsc, CTL_HI, count >> mem_width);
break;
case DMA_FROM_DEVICE:
channel_writel(gsc, CTL_HI, count >> reg_width);
break;
}
return 0;
}
EXPORT_SYMBOL(gsc3280_dma_set_dma_count);
inline dma_addr_t gsc3280_dma_get_src_addr(struct dma_chan *chan)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
return channel_readl(gsc, SAR);
}
EXPORT_SYMBOL(gsc3280_dma_get_src_addr);
inline dma_addr_t gsc3280_dma_get_dst_addr(struct dma_chan *chan)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
return channel_readl(gsc, DAR);
}
EXPORT_SYMBOL(gsc3280_dma_get_dst_addr);
inline int gsc3280_dma_get_tsblock(struct dma_chan *chan)
{
struct gsc3280_dma_chan * gsc = to_gsc3280_dma_chan(chan);
return (channel_readl(gsc,CTL_HI)) & 0xFFF;
}
EXPORT_SYMBOL(gsc3280_dma_get_tsblock);
/* called with gsc->lock held and all DMAC interrupts disabled */
static void gsc3280_handle_single(struct gsc3280_dma *gs, struct gsc3280_dma_chan *gsc,
u32 status_block, u32 status_err, u32 status_xfer)
{
unsigned long flags;
if (status_block & gsc->mask) {
void (*callback)(void *param);
void *callback_param;
// dev_vdbg(chan2dev(&gsc->chan), "new cyclic period llp 0x%08x\n",
// channel_readl(gsc, LLP));
// dma_writel(gs, CLEAR.BLOCK, gsc->mask);
callback = gsc->cdesc->period_callback;
callback_param = gsc->cdesc->period_callback_param;
if (callback)
callback(callback_param);
}
/*
* Error and transfer complete are highly unlikely, and will most
* likely be due to a configuration error by the user.
*/
if (unlikely(status_err & gsc->mask)) {
int i;
dev_err(chan2dev(&gsc->chan), "cyclic DMA unexpected %s "
"interrupt, stopping DMA transfer\n",
status_xfer ? "xfer" : "error");
spin_lock_irqsave(&gsc->lock, flags);
dev_err(chan2dev(&gsc->chan),
" SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
channel_readl(gsc, SAR),
channel_readl(gsc, DAR),
channel_readl(gsc, LLP),
channel_readl(gsc, CTL_HI),
channel_readl(gsc, CTL_LO));
channel_clear_bit(gs, CH_EN, gsc->mask);
while (dma_readl(gs, CH_EN) & gsc->mask)
cpu_relax();
/* make sure DMA does not restart by loading a new list */
channel_writel(gsc, LLP, 0);
channel_writel(gsc, CTL_LO, 0);
channel_writel(gsc, CTL_HI, 0);
dma_writel(gs, CLEAR.BLOCK, gsc->mask);
dma_writel(gs, CLEAR.ERROR, gsc->mask);
dma_writel(gs, CLEAR.XFER, gsc->mask);
for (i = 0; i < gsc->cdesc->periods; i++)
gsc3280_dump_lli(gsc, &gsc->cdesc->desc[i]->lli);
spin_unlock_irqrestore(&gsc->lock, flags);
}
if(unlikely(status_xfer & gsc->mask)){
// printk("enter the unlikely \n");
spin_lock_irqsave(&gsc->lock, flags);
/*
* Clear block interrupt flag before scanning so that we don't
* miss any, and read LLP before RAW_XFER to ensure it is
* valid if we decide to scan the list.
*/
dma_writel(gs, CLEAR.BLOCK, gsc->mask);
dma_writel(gs, CLEAR.XFER, gsc->mask);
spin_unlock_irqrestore(&gsc->lock, flags);
}
}
/* called with gsc->lock held and all DMAC interrupts disabled */
static void gsc3280_handle_cyclic(struct gsc3280_dma *gs, struct gsc3280_dma_chan *gsc,
u32 status_block, u32 status_err, u32 status_xfer)
{
unsigned long flags;
if (status_block & gsc->mask) {
void (*callback)(void *param);
void *callback_param;
dev_vdbg(chan2dev(&gsc->chan), "new cyclic period llp 0x%08x\n",
channel_readl(gsc, LLP));
dma_writel(gs, CLEAR.BLOCK, gsc->mask);
callback = gsc->cdesc->period_callback;
callback_param = gsc->cdesc->period_callback_param;
if (callback)
callback(callback_param);
}
/*
* Error and transfer complete are highly unlikely, and will most
* likely be due to a configuration error by the user.
*/
if (unlikely(status_err & gsc->mask) ||
unlikely(status_xfer & gsc->mask)) {
int i;
dev_err(chan2dev(&gsc->chan), "cyclic DMA unexpected %s "
"interrupt, stopping DMA transfer\n",
status_xfer ? "xfer" : "error");
spin_lock_irqsave(&gsc->lock, flags);
dev_err(chan2dev(&gsc->chan),
" SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
channel_readl(gsc, SAR),
channel_readl(gsc, DAR),
channel_readl(gsc, LLP),
channel_readl(gsc, CTL_HI),
channel_readl(gsc, CTL_LO));
channel_clear_bit(gs, CH_EN, gsc->mask);
while (dma_readl(gs, CH_EN) & gsc->mask)
cpu_relax();
/* make sure DMA does not restart by loading a new list */
channel_writel(gsc, LLP, 0);
channel_writel(gsc, CTL_LO, 0);
channel_writel(gsc, CTL_HI, 0);
dma_writel(gs, CLEAR.BLOCK, gsc->mask);
dma_writel(gs, CLEAR.ERROR, gsc->mask);
dma_writel(gs, CLEAR.XFER, gsc->mask);
for (i = 0; i < gsc->cdesc->periods; i++)
gsc3280_dump_lli(gsc, &gsc->cdesc->desc[i]->lli);
spin_unlock_irqrestore(&gsc->lock, flags);
}
}
/* ------------------------------------------------------------------------- */
static void gsc3280_dma_tasklet(unsigned long data)
{
struct gsc3280_dma *gs = (struct gsc3280_dma *)data;
struct gsc3280_dma_chan *gsc;
u32 status_block;
u32 status_xfer;
u32 status_err;
int i;
status_block = dma_readl(gs, RAW.BLOCK);
status_xfer = dma_readl(gs, RAW.XFER);
status_err = dma_readl(gs, RAW.ERROR);
// dev_vdbg(gs->dma.dev, "tasklet: status_block=%x status_err=%x\n",
// status_block, status_err);
// printk(KERN_ALERT"tasklet: status_block=%x status_err=%x status_xfer=%x\n",
// status_block, status_err, status_xfer);
for (i = 0; i < gs->dma.chancnt; i++) {
gsc = &gs->chan[i];
if (test_bit(GSC3280_DMA_IS_CYCLIC, &gsc->flags))
gsc3280_handle_cyclic(gs, gsc, status_block, status_err,
status_xfer);
else if (test_bit(GSC3280_DMA_IS_SINGLE, &gsc->flags))
gsc3280_handle_single(gs, gsc, status_block, status_err,
status_xfer);
else if (status_err & (1 << i))
gsc3280_handle_error(gs, gsc);
else if ((status_block | status_xfer) & (1 << i))
gsc3280_scan_descriptors(gs, gsc);
}
/*
* Re-enable interrupts. Block Complete interrupts are only
* enabled if the INT_EN bit in the descriptor is set. This
* will trigger a scan before the whole list is done.
*/
channel_set_bit(gs, MASK.XFER, gs->all_chan_mask);
channel_set_bit(gs, MASK.BLOCK, gs->all_chan_mask);
channel_set_bit(gs, MASK.ERROR, gs->all_chan_mask);
}
static irqreturn_t gsc3280_dma_interrupt(int irq, void *dev_id)
{
struct gsc3280_dma *gs = dev_id;
u32 status;
// dev_vdbg(gs->dma.dev, "interrupt: status=0x%x\n",
// dma_readl(gs, STATUS_INT));
/*
* Just disable the interrupts. We'll turn them back on in the
* softirq handler.
*/
channel_clear_bit(gs, MASK.XFER, gs->all_chan_mask);
channel_clear_bit(gs, MASK.BLOCK, gs->all_chan_mask);
channel_clear_bit(gs, MASK.ERROR, gs->all_chan_mask);
status = dma_readl(gs, STATUS_INT);
// printk("interrupts pending: 0x%x\n",status);
if (status) {
dev_err(gs->dma.dev,
"BUG: Unexpected interrupts pending: 0x%x\n",
status);
/* Try to recover */
channel_clear_bit(gs, MASK.XFER, (1 << 8) - 1);
channel_clear_bit(gs, MASK.BLOCK, (1 << 8) - 1);
channel_clear_bit(gs, MASK.SRC_TRAN, (1 << 8) - 1);
channel_clear_bit(gs, MASK.DST_TRAN, (1 << 8) - 1);
channel_clear_bit(gs, MASK.ERROR, (1 << 8) - 1);
}
tasklet_schedule(&gs->tasklet);
return IRQ_HANDLED;
}
/*----------------------------------------------------------------------*/
static dma_cookie_t gsc3280_tx_submit(struct dma_async_tx_descriptor *tx)
{
struct gsc3280_desc *desc = txd_to_gsc3280_desc(tx);
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(tx->chan);
dma_cookie_t cookie;
unsigned long flags;
spin_lock_irqsave(&gsc->lock, flags);
cookie = gsc3280_assign_cookie(gsc, desc);
/*
* REVISIT: We should attempt to chain as many descriptors as
* possible, perhaps even appending to those already submitted
* for DMA. But this is hard to do in a race-free manner.
*/
if (list_empty(&gsc->active_list)) {
dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
desc->txd.cookie);
} else {
dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
desc->txd.cookie);
list_add_tail(&desc->desc_node, &gsc->queue);
}
spin_unlock_irqrestore(&gsc->lock, flags);
return cookie;
}
static struct dma_async_tx_descriptor *
gsc3280_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
size_t len, unsigned long flags)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
struct gsc3280_desc *desc;
struct gsc3280_desc *first;
struct gsc3280_desc *prev;
size_t xfer_count;
size_t offset;
unsigned int src_width;
unsigned int dst_width;
u32 ctllo;
dev_vdbg(chan2dev(chan), "prep_dma_memcpy d0x%x s0x%x l0x%zx f0x%lx\n",
dest, src, len, flags);
if (unlikely(!len)) {
dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
return NULL;
}
/*
* We can be a lot more clever here, but this should take care
* of the most common optimization.
*/
if (!((src | dest | len) & 7))
src_width = dst_width = 3;
else if (!((src | dest | len) & 3))
src_width = dst_width = 2;
else if (!((src | dest | len) & 1))
src_width = dst_width = 1;
else
src_width = dst_width = 0;
ctllo = GSC3280_DEFAULT_CTLLO(chan->private)
| GSC3280_CTLL_DST_WIDTH(dst_width)
| GSC3280_CTLL_SRC_WIDTH(src_width)
| GSC3280_CTLL_DST_INC
| GSC3280_CTLL_SRC_INC
| GSC3280_CTLL_FC_M2M;
prev = first = NULL;
for (offset = 0; offset < len; offset += xfer_count << src_width) {
xfer_count = min_t(size_t, (len - offset) >> src_width,
GSC3280_MAX_COUNT);
desc = gsc3280_desc_get(gsc);
if (!desc)
goto err_desc_get;
desc->lli.sar = src + offset;
desc->lli.dar = dest + offset;
desc->lli.ctllo = ctllo;
desc->lli.ctlhi = xfer_count;
if (!first) {
first = desc;
} else {
prev->lli.llp = desc->txd.phys;
dma_sync_single_for_device(chan2parent(chan),
prev->txd.phys, sizeof(prev->lli),
DMA_TO_DEVICE);
list_add_tail(&desc->desc_node,
&first->tx_list);
}
prev = desc;
}
if (flags & DMA_PREP_INTERRUPT)
/* Trigger interrupt after last block */
prev->lli.ctllo |= GSC3280_CTLL_INT_EN;
prev->lli.llp = 0;
dma_sync_single_for_device(chan2parent(chan),
prev->txd.phys, sizeof(prev->lli),
DMA_TO_DEVICE);
first->txd.flags = flags;
first->len = len;
return &first->txd;
err_desc_get:
gsc3280_desc_put(gsc, first);
return NULL;
}
static struct dma_async_tx_descriptor *
gsc3280_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
unsigned int sg_len, enum dma_data_direction direction,
unsigned long flags)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
struct gsc3280_dma_slave *gss = chan->private;
struct gsc3280_desc *prev;
struct gsc3280_desc *first;
u32 ctllo;
dma_addr_t reg;
unsigned int reg_width;
unsigned int mem_width;
unsigned int i;
struct scatterlist *sg;
size_t total_len = 0;
dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
if (unlikely(!gss || !sg_len))
return NULL;
reg_width = gss->reg_width;
prev = first = NULL;
switch (direction) {
case DMA_TO_DEVICE:
ctllo = (GSC3280_DEFAULT_CTLLO(chan->private)
| GSC3280_CTLL_DST_WIDTH(reg_width)
| GSC3280_CTLL_DST_FIX
| GSC3280_CTLL_SRC_INC
| GSC3280_CTLL_FC(gss->fc));
reg = gss->tx_reg;
for_each_sg(sgl, sg, sg_len, i) {
struct gsc3280_desc *desc;
u32 len, dlen, mem;
mem = sg_phys(sg);
len = sg_dma_len(sg);
mem_width = 2;
if (unlikely(mem & 3 || len & 3))
mem_width = 0;
slave_sg_todev_fill_desc:
desc = gsc3280_desc_get(gsc);
if (!desc) {
dev_err(chan2dev(chan),
"not enough descriptors available\n");
goto err_desc_get;
}
desc->lli.sar = mem;
desc->lli.dar = reg;
desc->lli.ctllo = ctllo | GSC3280_CTLL_SRC_WIDTH(mem_width);
if ((len >> mem_width) > GSC3280_MAX_COUNT) {
dlen = GSC3280_MAX_COUNT << mem_width;
mem += dlen;
len -= dlen;
} else {
dlen = len;
len = 0;
}
desc->lli.ctlhi = dlen >> mem_width;
if (!first) {
first = desc;
} else {
prev->lli.llp = desc->txd.phys;
dma_sync_single_for_device(chan2parent(chan),
prev->txd.phys,
sizeof(prev->lli),
DMA_TO_DEVICE);
list_add_tail(&desc->desc_node,
&first->tx_list);
}
prev = desc;
total_len += dlen;
if (len)
goto slave_sg_todev_fill_desc;
}
break;
case DMA_FROM_DEVICE:
ctllo = (GSC3280_DEFAULT_CTLLO(chan->private)
| GSC3280_CTLL_SRC_WIDTH(reg_width)
| GSC3280_CTLL_DST_INC
| GSC3280_CTLL_SRC_FIX
| GSC3280_CTLL_FC(gss->fc));
reg = gss->rx_reg;
for_each_sg(sgl, sg, sg_len, i) {
struct gsc3280_desc *desc;
u32 len, dlen, mem;
mem = sg_phys(sg);
len = sg_dma_len(sg);
mem_width = 2;
if (unlikely(mem & 3 || len & 3))
mem_width = 0;
slave_sg_fromdev_fill_desc:
desc = gsc3280_desc_get(gsc);
if (!desc) {
dev_err(chan2dev(chan),
"not enough descriptors available\n");
goto err_desc_get;
}
desc->lli.sar = reg;
desc->lli.dar = mem;
desc->lli.ctllo = ctllo | GSC3280_CTLL_DST_WIDTH(mem_width);
if ((len >> reg_width) > GSC3280_MAX_COUNT) {
dlen = GSC3280_MAX_COUNT << reg_width;
mem += dlen;
len -= dlen;
} else {
dlen = len;
len = 0;
}
desc->lli.ctlhi = dlen >> reg_width;
if (!first) {
first = desc;
} else {
prev->lli.llp = desc->txd.phys;
dma_sync_single_for_device(chan2parent(chan),
prev->txd.phys,
sizeof(prev->lli),
DMA_TO_DEVICE);
list_add_tail(&desc->desc_node,
&first->tx_list);
}
prev = desc;
total_len += dlen;
if (len)
goto slave_sg_fromdev_fill_desc;
}
break;
default:
return NULL;
}
if (flags & DMA_PREP_INTERRUPT)
/* Trigger interrupt after last block */
prev->lli.ctllo |= GSC3280_CTLL_INT_EN;
prev->lli.llp = 0;
dma_sync_single_for_device(chan2parent(chan),
prev->txd.phys, sizeof(prev->lli),
DMA_TO_DEVICE);
first->len = total_len;
return &first->txd;
err_desc_get:
gsc3280_desc_put(gsc, first);
return NULL;
}
static int gsc3280_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
unsigned long arg)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
struct gsc3280_dma *gs = to_gsc3280_dma(chan->device);
struct gsc3280_desc *desc, *_desc;
unsigned long flags;
u32 cfglo;
LIST_HEAD(list);
if (cmd == DMA_PAUSE) {
spin_lock_irqsave(&gsc->lock, flags);
cfglo = channel_readl(gsc, CFG_LO);
channel_writel(gsc, CFG_LO, cfglo | GSC3280_CFGL_CH_SUSP);
while (!(channel_readl(gsc, CFG_LO) & GSC3280_CFGL_FIFO_EMPTY))
cpu_relax();
gsc->paused = true;
spin_unlock_irqrestore(&gsc->lock, flags);
} else if (cmd == DMA_RESUME) {
if (!gsc->paused)
return 0;
spin_lock_irqsave(&gsc->lock, flags);
cfglo = channel_readl(gsc, CFG_LO);
channel_writel(gsc, CFG_LO, cfglo & ~GSC3280_CFGL_CH_SUSP);
gsc->paused = false;
spin_unlock_irqrestore(&gsc->lock, flags);
} else if (cmd == DMA_TERMINATE_ALL) {
spin_lock_irqsave(&gsc->lock, flags);
channel_clear_bit(gs, CH_EN, gsc->mask);
while (dma_readl(gs, CH_EN) & gsc->mask)
cpu_relax();
gsc->paused = false;
/* active_list entries will end up before queued entries */
list_splice_init(&gsc->queue, &list);
list_splice_init(&gsc->active_list, &list);
spin_unlock_irqrestore(&gsc->lock, flags);
/* Flush all pending and queued descriptors */
list_for_each_entry_safe(desc, _desc, &list, desc_node)
gsc3280_descriptor_complete(gsc, desc, false);
} else
return -ENXIO;
return 0;
}
static enum dma_status
gsc3280_tx_status(struct dma_chan *chan,
dma_cookie_t cookie,
struct dma_tx_state *txstate)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
dma_cookie_t last_used;
dma_cookie_t last_complete;
int ret;
last_complete = gsc->completed;
last_used = chan->cookie;
ret = dma_async_is_complete(cookie, last_complete, last_used);
if (ret != DMA_SUCCESS) {
gsc3280_scan_descriptors(to_gsc3280_dma(chan->device), gsc);
last_complete = gsc->completed;
last_used = chan->cookie;
ret = dma_async_is_complete(cookie, last_complete, last_used);
}
if (ret != DMA_SUCCESS)
dma_set_tx_state(txstate, last_complete, last_used,
gsc3280_first_active(gsc)->len);
else
dma_set_tx_state(txstate, last_complete, last_used, 0);
if (gsc->paused)
return DMA_PAUSED;
return ret;
}
static void gsc3280_issue_pending(struct dma_chan *chan)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
if (!list_empty(&gsc->queue))
gsc3280_scan_descriptors(to_gsc3280_dma(chan->device), gsc);
}
static int gsc3280_alloc_chan_resources(struct dma_chan *chan)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
struct gsc3280_dma *gs = to_gsc3280_dma(chan->device);
struct gsc3280_desc *desc;
struct gsc3280_dma_slave *gss;
int i;
u32 cfghi;
u32 cfglo;
unsigned long flags;
dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
/* ASSERT: channel is idle */
if (dma_readl(gs, CH_EN) & gsc->mask) {
dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
return -EIO;
}
gsc->completed = chan->cookie = 1;
cfghi = GSC3280_CFGH_FIFO_MODE;
cfglo = 0;
gss = chan->private;
if (gss) {
/*
* We need controller-specific data to set up slave
* transfers.
*/
BUG_ON(!gss->dma_dev || gss->dma_dev != gs->dma.dev);
cfghi = gss->cfg_hi;
cfglo = gss->cfg_lo & ~GSC3280_CFGL_CH_PRIOR_MASK;
}
cfglo |= GSC3280_CFGL_CH_PRIOR(gsc->priority);
channel_writel(gsc, CFG_LO, cfglo);
channel_writel(gsc, CFG_HI, cfghi);
/*
* NOTE: some controllers may have additional features that we
* need to initialize here, like "scatter-gather" (which
* doesn't mean what you think it means), and status writeback.
*/
spin_lock_irqsave(&gsc->lock, flags);
i = gsc->descs_allocated;
while (gsc->descs_allocated < NR_DESCS_PER_CHANNEL) {
spin_unlock_irqrestore(&gsc->lock, flags);
desc = kzalloc(sizeof(struct gsc3280_desc), GFP_KERNEL);
if (!desc) {
dev_info(chan2dev(chan),
"only allocated %d descriptors\n", i);
spin_lock_irqsave(&gsc->lock, flags);
break;
}
INIT_LIST_HEAD(&desc->tx_list);
dma_async_tx_descriptor_init(&desc->txd, chan);
desc->txd.tx_submit = gsc3280_tx_submit;
desc->txd.flags = DMA_CTRL_ACK;
desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli,
sizeof(desc->lli), DMA_TO_DEVICE);
gsc3280_desc_put(gsc, desc);
spin_lock_irqsave(&gsc->lock, flags);
i = ++gsc->descs_allocated;
}
/* Enable interrupts */
channel_set_bit(gs, MASK.XFER, gsc->mask);
channel_set_bit(gs, MASK.BLOCK, gsc->mask);
channel_set_bit(gs, MASK.ERROR, gsc->mask);
spin_unlock_irqrestore(&gsc->lock, flags);
dev_dbg(chan2dev(chan),
"alloc_chan_resources allocated %d descriptors\n", i);
return i;
}
static void gsc3280_free_chan_resources(struct dma_chan *chan)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
struct gsc3280_dma *gs = to_gsc3280_dma(chan->device);
struct gsc3280_desc *desc, *_desc;
unsigned long flags;
LIST_HEAD(list);
dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
gsc->descs_allocated);
/* ASSERT: channel is idle */
BUG_ON(!list_empty(&gsc->active_list));
BUG_ON(!list_empty(&gsc->queue));
BUG_ON(dma_readl(to_gsc3280_dma(chan->device), CH_EN) & gsc->mask);
spin_lock_irqsave(&gsc->lock, flags);
list_splice_init(&gsc->free_list, &list);
gsc->descs_allocated = 0;
/* Disable interrupts */
channel_clear_bit(gs, MASK.XFER, gsc->mask);
channel_clear_bit(gs, MASK.BLOCK, gsc->mask);
channel_clear_bit(gs, MASK.ERROR, gsc->mask);
spin_unlock_irqrestore(&gsc->lock, flags);
list_for_each_entry_safe(desc, _desc, &list, desc_node) {
dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
dma_unmap_single(chan2parent(chan), desc->txd.phys,
sizeof(desc->lli), DMA_TO_DEVICE);
kfree(desc);
}
dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
}
/* --------------------- Cyclic DMA API extensions -------------------- */
/**
* gsc3280_dma_cyclic_start - start the cyclic DMA transfer
* @chan: the DMA channel to start
*
* Must be called with soft interrupts disabled. Returns zero on success or
* -errno on failure.
*/
int gsc3280_dma_cyclic_start(struct dma_chan *chan)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
struct gsc3280_dma *gs = to_gsc3280_dma(gsc->chan.device);
unsigned long flags;
if (!test_bit(GSC3280_DMA_IS_CYCLIC, &gsc->flags)) {
dev_err(chan2dev(&gsc->chan), "missing prep for cyclic DMA\n");
return -ENODEV;
}
spin_lock_irqsave(&gsc->lock, flags);
/* assert channel is idle */
if (dma_readl(gs, CH_EN) & gsc->mask) {
dev_err(chan2dev(&gsc->chan),
"BUG: Attempted to start non-idle channel\n");
dev_err(chan2dev(&gsc->chan),
" SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
channel_readl(gsc, SAR),
channel_readl(gsc, DAR),
channel_readl(gsc, LLP),
channel_readl(gsc, CTL_HI),
channel_readl(gsc, CTL_LO));
spin_unlock_irqrestore(&gsc->lock, flags);
return -EBUSY;
}
dma_writel(gs, CLEAR.BLOCK, gsc->mask);
dma_writel(gs, CLEAR.ERROR, gsc->mask);
dma_writel(gs, CLEAR.XFER, gsc->mask);
/* setup DMAC channel registers */
channel_writel(gsc, LLP, gsc->cdesc->desc[0]->txd.phys | 1);
// channel_writel(gsc, CTL_LO, GSC3280_CTLL_LLP_D_EN | GSC3280_CTLL_LLP_S_EN);
channel_writel(gsc, CTL_LO, GSC3280_CTLL_LLP_S_EN);
channel_writel(gsc, CTL_HI, 0);
channel_set_bit(gs, CH_EN, gsc->mask);
spin_unlock_irqrestore(&gsc->lock, flags);
return 0;
}
EXPORT_SYMBOL(gsc3280_dma_cyclic_start);
/**
* gsc3280_dma_cyclic_stop - stop the cyclic DMA transfer
* @chan: the DMA channel to stop
*
* Must be called with soft interrupts disabled.
*/
void gsc3280_dma_cyclic_stop(struct dma_chan *chan)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
struct gsc3280_dma *gs = to_gsc3280_dma(gsc->chan.device);
unsigned long flags;
spin_lock_irqsave(&gsc->lock, flags);
channel_clear_bit(gs, CH_EN, gsc->mask);
while (dma_readl(gs, CH_EN) & gsc->mask)
cpu_relax();
spin_unlock_irqrestore(&gsc->lock, flags);
}
EXPORT_SYMBOL(gsc3280_dma_cyclic_stop);
/**
* gsc3280_dma_cyclic_prep - prepare the cyclic DMA transfer
* @chan: the DMA channel to prepare
* @buf_addr: physical DMA address where the buffer starts
* @buf_len: total number of bytes for the entire buffer
* @period_len: number of bytes for each period
* @direction: transfer direction, to or from device
*
* Must be called before trying to start the transfer. Returns a valid struct
* gsc3280_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
*/
struct gsc3280_cyclic_desc *gsc3280_dma_cyclic_prep(struct dma_chan *chan,
dma_addr_t buf_addr, size_t buf_len, size_t period_len,
enum dma_data_direction direction)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
struct gsc3280_cyclic_desc *cdesc;
struct gsc3280_cyclic_desc *retval = NULL;
struct gsc3280_desc *desc;
struct gsc3280_desc *last = NULL;
struct gsc3280_dma_slave *gss = chan->private;
unsigned long was_cyclic;
unsigned int reg_width;
unsigned int mem_width;
unsigned int periods;
unsigned int i;
unsigned long flags;
spin_lock_irqsave(&gsc->lock, flags);
if (!list_empty(&gsc->queue) || !list_empty(&gsc->active_list)) {
spin_unlock_irqrestore(&gsc->lock, flags);
dev_dbg(chan2dev(&gsc->chan),
"queue and/or active list are not empty\n");
return ERR_PTR(-EBUSY);
}
was_cyclic = test_and_set_bit(GSC3280_DMA_IS_CYCLIC, &gsc->flags);
spin_unlock_irqrestore(&gsc->lock, flags);
if (was_cyclic) {
dev_dbg(chan2dev(&gsc->chan),
"channel already prepared for cyclic DMA\n");
return ERR_PTR(-EBUSY);
}
retval = ERR_PTR(-EINVAL);
reg_width = gss->reg_width;
mem_width = gss->mem_width;
periods = buf_len / period_len;
/* Check for too big/unaligned periods and unaligned DMA buffer. */
switch(direction) {
case DMA_TO_DEVICE:
if (period_len > (GSC3280_MAX_COUNT << mem_width))
goto out_err;
break;
case DMA_FROM_DEVICE:
if (period_len > (GSC3280_MAX_COUNT << reg_width))
goto out_err;
break;
default:
break;
}
if (unlikely(period_len & ((1 << reg_width) - 1)))
goto out_err;
if (unlikely(buf_addr & ((1 << reg_width) - 1)))
goto out_err;
if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE))))
goto out_err;
retval = ERR_PTR(-ENOMEM);
if (periods > NR_DESCS_PER_CHANNEL)
goto out_err;
cdesc = kzalloc(sizeof(struct gsc3280_cyclic_desc), GFP_KERNEL);
if (!cdesc)
goto out_err;
cdesc->desc = kzalloc(sizeof(struct gsc3280_desc *) * periods, GFP_KERNEL);
if (!cdesc->desc)
goto out_err_alloc;
for (i = 0; i < periods; i++) {
desc = gsc3280_desc_get(gsc);
if (!desc)
goto out_err_desc_get;
switch (direction) {
case DMA_TO_DEVICE:
channel_writel(gsc, DAR, gss->tx_reg);
desc->lli.dar = gss->tx_reg;
desc->lli.sar = buf_addr + (period_len * i);
desc->lli.ctllo = (GSC3280_DEFAULT_CTLLO(chan->private)
| GSC3280_CTLL_DST_WIDTH(reg_width)
| GSC3280_CTLL_SRC_WIDTH(mem_width)
| GSC3280_CTLL_DST_FIX
| GSC3280_CTLL_SRC_INC
| GSC3280_CTLL_FC(gss->fc)
| GSC3280_CTLL_INT_EN);
break;
case DMA_FROM_DEVICE:
desc->lli.dar = buf_addr + (period_len * i);
desc->lli.sar = gss->rx_reg;
desc->lli.ctllo = (GSC3280_DEFAULT_CTLLO(chan->private)
| GSC3280_CTLL_SRC_WIDTH(reg_width)
| GSC3280_CTLL_DST_WIDTH(mem_width)
| GSC3280_CTLL_DST_INC
| GSC3280_CTLL_SRC_FIX
| GSC3280_CTLL_FC(gss->fc)
| GSC3280_CTLL_INT_EN);
break;
default:
break;
}
desc->lli.ctlhi = (period_len >> reg_width);
cdesc->desc[i] = desc;
if (last) {
last->lli.llp = desc->txd.phys | 1;
dma_sync_single_for_device(chan2parent(chan),
last->txd.phys, sizeof(last->lli),
DMA_TO_DEVICE);
}
last = desc;
}
/* lets make a cyclic list */
last->lli.llp = cdesc->desc[0]->txd.phys | 1;
dma_sync_single_for_device(chan2parent(chan), last->txd.phys,
sizeof(last->lli), DMA_TO_DEVICE);
dev_dbg(chan2dev(&gsc->chan), "cyclic prepared buf 0x%08x len %zu "
"period %zu periods %d\n", buf_addr, buf_len,
period_len, periods);
cdesc->periods = periods;
gsc->cdesc = cdesc;
return cdesc;
out_err_desc_get:
while (i--)
gsc3280_desc_put(gsc, cdesc->desc[i]);
out_err_alloc:
kfree(cdesc);
out_err:
clear_bit(GSC3280_DMA_IS_CYCLIC, &gsc->flags);
return (struct gsc3280_cyclic_desc *)retval;
}
EXPORT_SYMBOL(gsc3280_dma_cyclic_prep);
/* for duyf */
void gsc3280_dma_set_cyclic_llp(struct dma_chan *chan, struct gsc3280_cyclic_desc * cdesc)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
channel_writel(gsc, LLP, cdesc->desc[0]->txd.phys | 1);
}
EXPORT_SYMBOL(gsc3280_dma_set_cyclic_llp);
/**
* gsc3280_dma_cyclic_free - free a prepared cyclic DMA transfer
* @chan: the DMA channel to free
*/
void gsc3280_dma_cyclic_free(struct dma_chan *chan)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
struct gsc3280_dma *gs = to_gsc3280_dma(gsc->chan.device);
struct gsc3280_cyclic_desc *cdesc = gsc->cdesc;
int i;
unsigned long flags;
dev_dbg(chan2dev(&gsc->chan), "cyclic free\n");
if (!cdesc)
return;
spin_lock_irqsave(&gsc->lock, flags);
channel_clear_bit(gs, CH_EN, gsc->mask);
while (dma_readl(gs, CH_EN) & gsc->mask)
cpu_relax();
dma_writel(gs, CLEAR.BLOCK, gsc->mask);
dma_writel(gs, CLEAR.ERROR, gsc->mask);
dma_writel(gs, CLEAR.XFER, gsc->mask);
spin_unlock_irqrestore(&gsc->lock, flags);
for (i = 0; i < cdesc->periods; i++)
gsc3280_desc_put(gsc, cdesc->desc[i]);
kfree(cdesc->desc);
kfree(cdesc);
clear_bit(GSC3280_DMA_IS_CYCLIC, &gsc->flags);
}
EXPORT_SYMBOL(gsc3280_dma_cyclic_free);
/*----------------------------------------------------------------------*/
/* --------------------- Single DMA API extensions -------------------- */
/**
* gsc3280_dma_single_start - start the single DMA transfer
* @chan: the DMA channel to start
*
* Must be called with soft interrupts disabled. Returns zero on success or
* -errno on failure.
*/
int gsc3280_dma_single_start(struct dma_chan *chan)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
struct gsc3280_dma *gs = to_gsc3280_dma(gsc->chan.device);
unsigned long flags;
if (!test_bit(GSC3280_DMA_IS_SINGLE, &gsc->flags)) {
dev_err(chan2dev(&gsc->chan), "missing prep for single DMA\n");
return -ENODEV;
}
spin_lock_irqsave(&gsc->lock, flags);
/* assert channel is idle */
if (dma_readl(gs, CH_EN) & gsc->mask) {
dev_err(chan2dev(&gsc->chan),
"BUG: Attempted to start non-idle channel\n");
dev_err(chan2dev(&gsc->chan),
" SAR: 0x%x DAR: 0x%x CTL: 0x%x:%08x\n",
channel_readl(gsc, SAR),
channel_readl(gsc, DAR),
channel_readl(gsc, CTL_HI),
channel_readl(gsc, CTL_LO));
spin_unlock_irqrestore(&gsc->lock, flags);
return -EBUSY;
}
dma_writel(gs, CLEAR.BLOCK, gsc->mask);
dma_writel(gs, CLEAR.ERROR, gsc->mask);
dma_writel(gs, CLEAR.XFER, gsc->mask);
/* setup DMAC channel registers */
// channel_writel(gsc, CTL_LO, channel_readl(gsc, CTL_LO) | GSC3280_CTLL_LLP_S_EN);
// channel_writel(gsc, CTL_LO, 0x12100922 | 1);
// channel_writel(gsc, CTL_HI, 0);
// channel_writel(gsc, CTL_HI, (PAGE_SIZE/2)/4);
// channel_writel(gsc, SAR, 0x1c1121c8); // FIXME
// channel_writel(gsc, DAR, 0x1c1121c8);
#if 0
printk(
" SAR: 0x%x DAR: 0x%x CTL: 0x%x:%08x CFG:0x%x:%08x\n",
channel_readl(gsc, SAR),
channel_readl(gsc, DAR),
channel_readl(gsc, CTL_HI),
channel_readl(gsc, CTL_LO),
channel_readl(gsc, CFG_HI),
channel_readl(gsc, CFG_LO)
);
#endif
channel_set_bit(gs, CH_EN, gsc->mask);
spin_unlock_irqrestore(&gsc->lock, flags);
return 0;
}
EXPORT_SYMBOL(gsc3280_dma_single_start);
/**
* gsc3280_dma_single_stop - stop the single DMA transfer
* @chan: the DMA channel to stop
*
* Must be called with soft interrupts disabled.
*/
void gsc3280_dma_single_stop(struct dma_chan *chan)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
struct gsc3280_dma *gs = to_gsc3280_dma(gsc->chan.device);
unsigned long flags;
spin_lock_irqsave(&gsc->lock, flags);
channel_clear_bit(gs, CH_EN, gsc->mask);
while (dma_readl(gs, CH_EN) & gsc->mask)
cpu_relax();
spin_unlock_irqrestore(&gsc->lock, flags);
}
EXPORT_SYMBOL(gsc3280_dma_single_stop);
/**
* gsc3280_dma_single_prep - prepare the single DMA transfer
* @chan: the DMA channel to prepare
* @buf_addr: physical DMA address where the buffer starts
* @buf_len: total number of bytes for the entire buffer
* @period_len: number of bytes for each period
* @direction: transfer direction, to or from device
*
* Must be called before trying to start the transfer. Returns a valid struct
* gsc3280_single_desc if successful or an ERR_PTR(-errno) if not successful.
*/
struct gsc3280_cyclic_desc *gsc3280_dma_single_prep(struct dma_chan *chan,
dma_addr_t buf_addr, size_t buf_len,
enum dma_data_direction direction)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
struct gsc3280_cyclic_desc *cdesc;
struct gsc3280_cyclic_desc *retval = NULL;
struct gsc3280_desc *desc;
struct gsc3280_dma_slave *gss = chan->private;
unsigned int reg_width;
unsigned int mem_width;
unsigned long flags;
test_and_set_bit(GSC3280_DMA_IS_SINGLE, &gsc->flags);
spin_lock_irqsave(&gsc->lock, flags);
if (!list_empty(&gsc->queue) || !list_empty(&gsc->active_list)) {
spin_unlock_irqrestore(&gsc->lock, flags);
dev_dbg(chan2dev(&gsc->chan),
"queue and/or active list are not empty\n");
return ERR_PTR(-EBUSY);
}
spin_unlock_irqrestore(&gsc->lock, flags);
retval = ERR_PTR(-EINVAL);
reg_width = gss->reg_width;
mem_width = gss->mem_width;
if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE))))
goto out_err;
/* Check for too big/unaligned periods and unaligned DMA buffer. */
switch (direction) {
case DMA_TO_DEVICE:
if (unlikely(buf_addr & ((1 << mem_width) - 1)))
goto out_err;
break;
case DMA_FROM_DEVICE:
if (unlikely(buf_addr & ((1 << reg_width) - 1)))
goto out_err;
break;
default:
break;
}
retval = ERR_PTR(-ENOMEM);
cdesc = kzalloc(sizeof(struct gsc3280_cyclic_desc), GFP_KERNEL);
if (!cdesc)
goto out_err;
cdesc->desc = kzalloc(sizeof(struct gsc3280_desc *) , GFP_KERNEL);
if (!cdesc->desc)
goto out_err_alloc;
desc = gsc3280_desc_get(gsc);
if (!desc)
goto out_err_desc_get;
switch (direction) {
case DMA_TO_DEVICE:
channel_writel(gsc,SAR,buf_addr);
channel_writel(gsc,DAR,gss->tx_reg);
desc->lli.ctllo = (GSC3280_DEFAULT_CTLLO(chan->private)
| GSC3280_CTLL_DST_WIDTH(reg_width)
| GSC3280_CTLL_SRC_WIDTH(mem_width)
| GSC3280_CTLL_DST_FIX
| GSC3280_CTLL_SRC_INC
| GSC3280_CTLL_FC(gss->fc)
| GSC3280_CTLL_INT_EN);
desc->lli.ctllo &= ~(GSC3280_CTLL_LLP_D_EN | GSC3280_CTLL_LLP_S_EN);
channel_writel(gsc, CTL_LO, desc->lli.ctllo | 1);
break;
case DMA_FROM_DEVICE:
channel_writel(gsc,DAR,buf_addr);
channel_writel(gsc,SAR,gss->rx_reg);
desc->lli.ctllo = (GSC3280_DEFAULT_CTLLO(chan->private)
| GSC3280_CTLL_SRC_WIDTH(reg_width)
| GSC3280_CTLL_DST_WIDTH(mem_width)
| GSC3280_CTLL_DST_INC
| GSC3280_CTLL_SRC_FIX
| GSC3280_CTLL_FC(gss->fc)
| GSC3280_CTLL_INT_EN);
desc->lli.ctllo &= ~(GSC3280_CTLL_LLP_D_EN | GSC3280_CTLL_LLP_S_EN);
channel_writel(gsc, CTL_LO, desc->lli.ctllo | 1);
break;
default:
break;
}
cdesc->desc[0] = desc;
desc->lli.ctlhi = (buf_len >> reg_width);
channel_writel(gsc, CTL_HI, desc->lli.ctlhi);
dma_sync_single_for_device(chan2parent(chan), desc->txd.phys,
sizeof(desc->lli), DMA_TO_DEVICE);
cdesc->periods = 0;
gsc->cdesc = cdesc;
return cdesc;
out_err_desc_get:
gsc3280_desc_put(gsc, cdesc->desc[0]);
out_err_alloc:
kfree(cdesc);
out_err:
clear_bit(GSC3280_DMA_IS_SINGLE, &gsc->flags);
return (struct gsc3280_cyclic_desc *)retval;
}
EXPORT_SYMBOL(gsc3280_dma_single_prep);
/**
* gsc3280_dma_single_free - free a prepared single DMA transfer
* @chan: the DMA channel to free
*/
void gsc3280_dma_single_free(struct dma_chan *chan)
{
struct gsc3280_dma_chan *gsc = to_gsc3280_dma_chan(chan);
struct gsc3280_dma *gs = to_gsc3280_dma(gsc->chan.device);
struct gsc3280_cyclic_desc *cdesc = gsc->cdesc;
unsigned long flags;
dev_dbg(chan2dev(&gsc->chan), "single free\n");
if (!cdesc)
return;
spin_lock_irqsave(&gsc->lock, flags);
channel_clear_bit(gs, CH_EN, gsc->mask);
while (dma_readl(gs, CH_EN) & gsc->mask)
cpu_relax();
dma_writel(gs, CLEAR.BLOCK, gsc->mask);
dma_writel(gs, CLEAR.ERROR, gsc->mask);
dma_writel(gs, CLEAR.XFER, gsc->mask);
spin_unlock_irqrestore(&gsc->lock, flags);
gsc3280_desc_put(gsc, cdesc->desc[0]);
kfree(cdesc->desc);
kfree(cdesc);
clear_bit(GSC3280_DMA_IS_SINGLE, &gsc->flags);
}
EXPORT_SYMBOL(gsc3280_dma_single_free);
/*----------------------------------------------------------------------*/
static void gsc3280_dma_off(struct gsc3280_dma *gs)
{
dma_writel(gs, CFG, 0);
channel_clear_bit(gs, MASK.XFER, gs->all_chan_mask);
channel_clear_bit(gs, MASK.BLOCK, gs->all_chan_mask);
channel_clear_bit(gs, MASK.SRC_TRAN, gs->all_chan_mask);
channel_clear_bit(gs, MASK.DST_TRAN, gs->all_chan_mask);
channel_clear_bit(gs, MASK.ERROR, gs->all_chan_mask);
while (dma_readl(gs, CFG) & GSC3280_CFG_DMA_EN)
cpu_relax();
}
static int __init gsc3280_probe(struct platform_device *pdev)
{
struct gsc3280_dma_platform_data *pdata;
struct resource *io;
struct gsc3280_dma *gs;
size_t size;
int irq;
int err;
int i;
pdata = pdev->dev.platform_data;
if (!pdata || pdata->nr_channels > GSC3280_DMA_MAX_NR_CHANNELS)
return -EINVAL;
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!io)
return -EINVAL;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
size = sizeof(struct gsc3280_dma);
size += pdata->nr_channels * sizeof(struct gsc3280_dma_chan);
gs = kzalloc(size, GFP_KERNEL);
if (!gs)
return -ENOMEM;
if (!request_mem_region(io->start, GSC3280_REGLEN, pdev->dev.driver->name)) {
err = -EBUSY;
goto err_kfree;
}
gs->regs = ioremap(io->start, GSC3280_REGLEN);
if (!gs->regs) {
err = -ENOMEM;
goto err_release_r;
}
gs->clk = clk_get(&pdev->dev, "dma");
if (IS_ERR(gs->clk)) {
err = PTR_ERR(gs->clk);
goto err_clk;
}
clk_enable(gs->clk);
/* force dma off, just in case */
gsc3280_dma_off(gs);
err = request_irq(irq, gsc3280_dma_interrupt, 0, "gsc3280_dmac", gs);
if (err)
goto err_irq;
platform_set_drvdata(pdev, gs);
tasklet_init(&gs->tasklet, gsc3280_dma_tasklet, (unsigned long)gs);
gs->all_chan_mask = (1 << pdata->nr_channels) - 1;
INIT_LIST_HEAD(&gs->dma.channels);
for (i = 0; i < pdata->nr_channels; i++, gs->dma.chancnt++) {
struct gsc3280_dma_chan *gsc = &gs->chan[i];
gsc->chan.device = &gs->dma;
gsc->chan.cookie = gsc->completed = 1;
gsc->chan.chan_id = i;
if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
list_add_tail(&gsc->chan.device_node,
&gs->dma.channels);
else
list_add(&gsc->chan.device_node, &gs->dma.channels);
/* 7 is highest priority & 0 is lowest. */
if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
gsc->priority = 7 - i;
else
gsc->priority = i;
gsc->ch_regs = &__gsc3280_regs(gs)->CHAN[i];
spin_lock_init(&gsc->lock);
gsc->mask = 1 << i;
INIT_LIST_HEAD(&gsc->active_list);
INIT_LIST_HEAD(&gsc->queue);
INIT_LIST_HEAD(&gsc->free_list);
channel_clear_bit(gs, CH_EN, gsc->mask);
}
/* Clear/disable all interrupts on all channels. */
dma_writel(gs, CLEAR.XFER, gs->all_chan_mask);
dma_writel(gs, CLEAR.BLOCK, gs->all_chan_mask);
dma_writel(gs, CLEAR.SRC_TRAN, gs->all_chan_mask);
dma_writel(gs, CLEAR.DST_TRAN, gs->all_chan_mask);
dma_writel(gs, CLEAR.ERROR, gs->all_chan_mask);
channel_clear_bit(gs, MASK.XFER, gs->all_chan_mask);
channel_clear_bit(gs, MASK.BLOCK, gs->all_chan_mask);
channel_clear_bit(gs, MASK.SRC_TRAN, gs->all_chan_mask);
channel_clear_bit(gs, MASK.DST_TRAN, gs->all_chan_mask);
channel_clear_bit(gs, MASK.ERROR, gs->all_chan_mask);
dma_cap_set(DMA_MEMCPY, gs->dma.cap_mask);
dma_cap_set(DMA_SLAVE, gs->dma.cap_mask);
if (pdata->is_private)
dma_cap_set(DMA_PRIVATE, gs->dma.cap_mask);
gs->dma.dev = &pdev->dev;
gs->dma.device_alloc_chan_resources = gsc3280_alloc_chan_resources;
gs->dma.device_free_chan_resources = gsc3280_free_chan_resources;
gs->dma.device_prep_dma_memcpy = gsc3280_prep_dma_memcpy;
gs->dma.device_prep_slave_sg = gsc3280_prep_slave_sg;
gs->dma.device_control = gsc3280_control;
gs->dma.device_tx_status = gsc3280_tx_status;
gs->dma.device_issue_pending = gsc3280_issue_pending;
dma_writel(gs, CFG, GSC3280_CFG_DMA_EN);
printk(KERN_INFO "%s: GSC3280 DMA Controller, %d channels\n",
dev_name(&pdev->dev), gs->dma.chancnt);
dma_async_device_register(&gs->dma);
return 0;
err_irq:
clk_disable(gs->clk);
clk_put(gs->clk);
err_clk:
iounmap(gs->regs);
gs->regs = NULL;
err_release_r:
release_resource(io);
err_kfree:
kfree(gs);
return err;
}
static int __exit gsc3280_remove(struct platform_device *pdev)
{
struct gsc3280_dma *gs = platform_get_drvdata(pdev);
struct gsc3280_dma_chan *gsc, *_gsc;
struct resource *io;
gsc3280_dma_off(gs);
dma_async_device_unregister(&gs->dma);
free_irq(platform_get_irq(pdev, 0), gs);
tasklet_kill(&gs->tasklet);
list_for_each_entry_safe(gsc, _gsc, &gs->dma.channels,
chan.device_node) {
list_del(&gsc->chan.device_node);
channel_clear_bit(gs, CH_EN, gsc->mask);
}
clk_disable(gs->clk);
clk_put(gs->clk);
iounmap(gs->regs);
gs->regs = NULL;
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(io->start, GSC3280_REGLEN);
kfree(gs);
return 0;
}
static void gsc3280_shutdown(struct platform_device *pdev)
{
struct gsc3280_dma *gs = platform_get_drvdata(pdev);
gsc3280_dma_off(platform_get_drvdata(pdev));
clk_disable(gs->clk);
}
static int gsc3280_suspend_noirq(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct gsc3280_dma *gs = platform_get_drvdata(pdev);
gsc3280_dma_off(platform_get_drvdata(pdev));
clk_disable(gs->clk);
return 0;
}
static int gsc3280_resume_noirq(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct gsc3280_dma *gs = platform_get_drvdata(pdev);
clk_enable(gs->clk);
dma_writel(gs, CFG, GSC3280_CFG_DMA_EN);
return 0;
}
static const struct dev_pm_ops gsc3280_dev_pm_ops = {
.suspend_noirq = gsc3280_suspend_noirq,
.resume_noirq = gsc3280_resume_noirq,
};
static struct platform_driver gsc3280_driver = {
.remove = __exit_p(gsc3280_remove),
.shutdown = gsc3280_shutdown,
.driver = {
.name = "gsc3280_dmac",
.pm = &gsc3280_dev_pm_ops,
},
};
static int __init gsc3280_init(void)
{
return platform_driver_probe(&gsc3280_driver, gsc3280_probe);
}
subsys_initcall(gsc3280_init);
static void __exit gsc3280_exit(void)
{
platform_driver_unregister(&gsc3280_driver);
}
module_exit(gsc3280_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
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