301 lines
7.4 KiB
C
301 lines
7.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
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*
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* Copyright (C) 2009 Lemote, Inc.
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* Author: Yan hua (yanhua@lemote.com)
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* Author: Wu Zhangjin (wuzhangjin@gmail.com)
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*/
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/serial_8250.h>
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#include <gsc3280/gsc3280_regs.h>
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#include <asm/bootinfo.h>
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#include <loongson.h>
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#include <machine.h>
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#include <gsc3280/gsc3280_int.h>
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#include <linux/clk.h>
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int printf_raw(const char *fmt, ...);
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#if 0
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#define PORT(int) \
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{ \
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.irq = int, \
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.uartclk = 1843200, \
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.iotype = UPIO_PORT, \
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \
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.regshift = 0, \
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}
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#define UART0_CLK 5560000
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#define UART1_CLK 5560000
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#define UART2_CLK 5560000
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#define UART3_CLK 16670000
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#define UART4_CLK 16670000
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#define UART5_CLK 16670000
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#define UART6_CLK 5560000
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#define UART7_CLK 5560000
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#define PORT_M(int) \
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{ \
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.irq = MIPS_CPU_IRQ_BASE + 8 + (int), \
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.uartclk = UART_CLK, \
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.iotype = UPIO_MEM, \
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.flags = UPF_BUGGY_UART | UPF_SKIP_TEST, \
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.membase = (void __iomem *)NULL, \
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.regshift = 0, \
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.private_data = &serial_data, \
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}
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#endif
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//extern struct serial_platform_data serial_data;
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int uart0=0;
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int uart1=1;
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int uart2=2;
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int uart3=3;
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int uart4=4;
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int uart5=5;
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int uart6=6;
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int uart7=7;
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//static const unsigned int U0_CLK=2*clk_get_rate(clk_get(NULL,"uart0"));
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//#define CLK0 (2*clk_get_rate(clk_get(NULL,"uart0")))
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static struct plat_serial8250_port uart8250_uart0_data[]={
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{
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.membase= NULL,
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.mapbase=GSC3280_UART0_BASEADDR & 0x1fffffff,
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.irq =EXT_GSC3280_UART0_IRQ,
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//uartclk =2*clk_get_rate(clk_get(NULL,"uart0")),
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//.uartclk =11120000,
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.regshift = 0,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST|UPF_IOREMAP,
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.private_data =&uart0,
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},
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{}
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};
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static struct plat_serial8250_port uart8250_uart1_data[]={
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{
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.membase= NULL,
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.mapbase=GSC3280_UART1_BASEADDR & 0x1fffffff,
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.irq =EXT_GSC3280_UART1_IRQ,
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// .uartclk =5560000,
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// .uartclk =11120000,
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.regshift = 0,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST|UPF_IOREMAP,
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.private_data=&uart1,
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// .private_data = &serial_data,
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},
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{}
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};
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static struct plat_serial8250_port uart8250_uart2_data[]={
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{
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.membase= NULL,
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.mapbase=GSC3280_UART2_BASEADDR & 0x1fffffff,
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.irq =EXT_GSC3280_UART2_IRQ,
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//.uartclk =5560000,
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// .uartclk =11120000,
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.regshift = 0,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST|UPF_IOREMAP,
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.private_data=&uart2,
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// .private_data = &serial_data,
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},
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{}
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};
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static struct plat_serial8250_port uart8250_uart3_data[]={
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{
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.membase= NULL,
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.mapbase=GSC3280_UART3_BASEADDR & 0x1fffffff,
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.irq =EXT_GSC3280_UART3_IRQ,
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//.uartclk =16670000,
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// .uartclk =33340000,
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.regshift = 0,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST|UPF_IOREMAP,
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.private_data=&uart3,
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// .private_data = &serial_data,
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},
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{}
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};
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static struct plat_serial8250_port uart8250_uart4_data[]={
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{
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.membase= NULL,
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.mapbase=GSC3280_UART4_BASEADDR & 0x1fffffff,
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//.uartclk =16670000,
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.irq =EXT_GSC3280_UART4_IRQ,
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// .uartclk =33340000,
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.regshift = 0,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST|UPF_IOREMAP,
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.private_data=&uart4,
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// .private_data = &serial_data,
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},
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{}
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};
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static struct plat_serial8250_port uart8250_uart5_data[]={
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{
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.membase= NULL,
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.mapbase=GSC3280_UART5_BASEADDR & 0x1fffffff,
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.irq =EXT_GSC3280_UART5_IRQ,
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//.uartclk =16670000,
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// .uartclk =33340000,
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.regshift = 0,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST|UPF_IOREMAP,
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.private_data=&uart5,
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// .private_data = &serial_data,
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},
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{}
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};
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static struct plat_serial8250_port uart8250_uart6_data[]={
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{
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.membase= NULL,
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.mapbase=GSC3280_UART6_BASEADDR & 0x1fffffff,
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.irq =EXT_GSC3280_UART6_IRQ,
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//.uartclk =921600,
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//.uartclk =463333,
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// .uartclk =5560000,
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.regshift = 0,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST|UPF_IOREMAP,
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.private_data=&uart6,
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// .private_data = &serial_data,
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},
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{}
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};
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static struct plat_serial8250_port uart8250_uart7_data[]={
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{
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.membase= NULL,
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.mapbase=GSC3280_UART7_BASEADDR & 0x1fffffff,
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.irq =EXT_GSC3280_UART7_IRQ,
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// .uartclk =5560000,
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.regshift = 0,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST|UPF_IOREMAP,
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.private_data=&uart7,
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// .private_data = &serial_data,
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},
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{}
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};
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static struct platform_device uart8250_uart0_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev={
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.platform_data=(void *)uart8250_uart0_data,
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}
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};
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static struct platform_device uart8250_uart1_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM1,
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.dev={
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.platform_data=(void *)uart8250_uart1_data,
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}
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};
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static struct platform_device uart8250_uart2_device = {
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.name = "serial8250",
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.id =PLAT8250_DEV_PLATFORM2,
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.dev={
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.platform_data=(void *)uart8250_uart2_data,
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}
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};
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static struct platform_device uart8250_uart3_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM3,
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.dev={
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.platform_data=(void *)uart8250_uart3_data,
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}
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};
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static struct platform_device uart8250_uart4_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM4,
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.dev={
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.platform_data=(void *)uart8250_uart4_data,
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}
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};
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static struct platform_device uart8250_uart5_device = {
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.name = "serial8250",
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.id =PLAT8250_DEV_PLATFORM5,
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.dev={
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.platform_data=(void *)uart8250_uart5_data,
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}
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};
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static struct platform_device uart8250_uart6_device = {
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.name = "serial8250",
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.id =PLAT8250_DEV_PLATFORM6,
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.dev={
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.platform_data=(void *)uart8250_uart6_data,
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}
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};
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static struct platform_device uart8250_uart7_device = {
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.name = "serial8250",
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.id =PLAT8250_DEV_PLATFORM7,
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.dev={
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.platform_data=(void *)uart8250_uart7_data,
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}
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};
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void serial_get_clk(void)
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{
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uart8250_uart0_data->uartclk=clk_get_rate(clk_get(NULL,"uart0"))<<1;
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uart8250_uart1_data->uartclk=clk_get_rate(clk_get(NULL,"uart1"))<<1;
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uart8250_uart2_data->uartclk=clk_get_rate(clk_get(NULL,"uart2"))<<1;
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uart8250_uart3_data->uartclk=clk_get_rate(clk_get(NULL,"uart3"))<<1;
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uart8250_uart4_data->uartclk=clk_get_rate(clk_get(NULL,"uart4"))<<1;
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uart8250_uart5_data->uartclk=clk_get_rate(clk_get(NULL,"uart5"))<<1;
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uart8250_uart6_data->uartclk=clk_get_rate(clk_get(NULL,"uart6"));
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uart8250_uart7_data->uartclk=clk_get_rate(clk_get(NULL,"uart7"));
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}
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static int __init serial_init(void)
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{
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int i;
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for(i=0;i<8;i++){
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if(9 == readl((volatile void*)(GSC3280_REGADDR_SYSCTL_CLKDIV_UART0 + (i*0x4)))){
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writel(0x1,(volatile void*)(GSC3280_REGADDR_SYSCTL_CLKDIV_UART0 + (i*0x4)));
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}
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printk(KERN_INFO "KERN uart%d clk div: 0X%08x\n",i,readl((volatile void*)(GSC3280_REGADDR_SYSCTL_CLKDIV_UART0 + (i*0x4))));
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}
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serial_get_clk();
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platform_device_register(&uart8250_uart0_device);
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platform_device_register(&uart8250_uart1_device);
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platform_device_register(&uart8250_uart2_device);
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platform_device_register(&uart8250_uart3_device);
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platform_device_register(&uart8250_uart4_device);
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platform_device_register(&uart8250_uart5_device);
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platform_device_register(&uart8250_uart6_device);
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platform_device_register(&uart8250_uart7_device);
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return 0;
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}
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device_initcall(serial_init);
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