437 lines
9.9 KiB
C
437 lines
9.9 KiB
C
/*
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* GSC3280 SoC adc Controller Driver
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*
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* Copyright (C) 2013 BLX IC Design Corp.,Ltd.
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* Author: Davied, apple_guet@126.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/list.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/adc-core.h>
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#include <linux/spi/gsc3280_spi.h>
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#ifdef CONFIG_GSC3280_ADC_DEBUG
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#define DBG(msg...) do { \
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printk(KERN_INFO msg); \
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} while (0)
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#else
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#define DBG(msg...) do { } while(0)
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#endif
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#define GSC_SYS_CTL_RST0_REG *(volatile unsigned int *)0xbc04a010
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#define SYS_CTL_RST0_ADC_TS BIT(3)
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//adc cmd state
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#define GSC_ADC_CMD_TX_NOW 0x00
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#define GSC_ADC_CMD_IDLE 0x08
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#define GSC_ADC_CMD_SUSPEND 0x09
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#define GSC_ADC_CMD_BUSY 0x0f
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//adc date state
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#define GSC_ADC_VAL_DATE 0x00
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#define GSC_ADC_BUSY 0x0f
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//ret value
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#define SPI_BUSY -1
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#define WRITE_DATE_ERR -2
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#define READ_DATE_ERR -3
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#define CMD_ERR -4
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#define RESULT_ERR -5
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#define MAX_WAIT_CNT 60000
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#define GSC3280_ADC_NAME "gsc-adc"
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typedef enum {
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TX_FIFO_NO_FULL,
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TX_FIFO_EMPTY,
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RX_FIFO_NO_EMPTY,
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RX_FIFO_FULL,
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BUSY,
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FREE,
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SEND_OK,
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READ_OK
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} spi_state_e;
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struct gsc_adc_dev {
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char name[20];
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int irq;
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struct clk *clk;
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spinlock_t lock;
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void __iomem *regs;
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int result;
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unsigned short cmd;
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struct list_head device_entry;
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struct platform_device *pdev;
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struct adc_core_dev *adc_dev;
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};
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static LIST_HEAD(gsc3280_adc_list);
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static DEFINE_MUTEX(gsc3280_adc_list_lock);
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//ret: 1:busy, 0:free
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static int getSpiState(struct gsc_adc_dev *adc)
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{
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unsigned int time_cnt = 0;
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while (readl(adc->regs + GSC_SPI_SR) & GSC_SPI_SR_BUSY) {
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if (time_cnt++ > MAX_WAIT_CNT) {
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DBG("spi busy, stat = %x\n", readl(adc->regs + GSC_SPI_SR));
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return SPI_BUSY;
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}
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}
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return 0;
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}
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static int writeSpiDate(struct gsc_adc_dev *adc)
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{
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int cnt = 0, stat = 0;
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stat = getSpiState(adc);
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if (stat != 0) {
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DBG("in write spi date,spi is busy\n");
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return stat;
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}
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//spi0 fifo can write, transmit fifo empty
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while (!(readl(adc->regs + GSC_SPI_SR) & GSC_SPI_SR_TX_NO_FULL)) {
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if (cnt++ > MAX_WAIT_CNT) {
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DBG("write spi date error, stat = %x\n", readl(adc->regs + GSC_SPI_SR));
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return WRITE_DATE_ERR;
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}
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}
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writel(adc->cmd, adc->regs + GSC_SPI_DA_S);
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return 0;
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}
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/* prepare to read data from adc */
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static int readSpiDate(struct gsc_adc_dev *adc)
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{
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int cnt= 0, stat = 0;
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stat = getSpiState(adc);
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if (stat < 0) {
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DBG("in read spi date,spi is busy\n");
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return stat;
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}
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//spi0 fifo receive not empty
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while (!(readl(adc->regs + GSC_SPI_SR) & GSC_SPI_SR_RX_N_EMPTY)) {
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if (cnt++ > MAX_WAIT_CNT) {
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DBG("read spi date error, spi stat = %x\n", readl(adc->regs + GSC_SPI_SR));
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return READ_DATE_ERR;
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}
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}
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adc->result = (unsigned short)readl(adc->regs + GSC_SPI_DA_S);
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return 0;
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}
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#if 0
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static void resetAdcTs(void)
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{
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GSC_SYS_CTL_RST0_REG |= SYS_CTL_RST0_ADC_TS;
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mdelay(1);
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GSC_SYS_CTL_RST0_REG &= ~SYS_CTL_RST0_ADC_TS;
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}
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#endif
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//return 0:date valid, other:date error
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static int gsc3280AdcCon(unsigned short cmd)
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{
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struct gsc_adc_dev *adc;
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int ret = 0, status = 0/*, cnt = 0*/;
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//DBG("gscAdcCon\n");
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mutex_lock(&gsc3280_adc_list_lock);
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list_for_each_entry(adc, &gsc3280_adc_list, device_entry) {
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if(strcmp(adc->name, GSC3280_ADC_NAME) == 0) {
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status = 0;
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break;
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}
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}
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mutex_unlock(&gsc3280_adc_list_lock);
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if (status != 0) {
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DBG("get gsc3280 adc struct error\n");
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return -5;
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}
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adc->cmd = cmd;
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#if 0
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resetAdcTs();
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while (cnt++ < MAX_CMD_NUM) {
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ret = writeSpiDate(client, CMD_GSC_ADC_IDLE);
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if (ret != 0)
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return ret;
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ret = readSpiDate(client);
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if(ret != 0)
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return ret;
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status = client->result >> 12;
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switch (client->result) {
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case GSC_ADC_CMD_TX_NOW:
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status = 1;
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break;
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case GSC_ADC_CMD_IDLE:
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status = 0; //send ok
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break;
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case GSC_ADC_CMD_SUSPEND:
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status = 2;
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break;
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case GSC_ADC_CMD_BUSY:
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status = 3;
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break;
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default:
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status = 4; //soft reset
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break;
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}
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if (status != 0)
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mdelay(1); //delay and go on while
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else
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break;
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}
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if (status != 0) {
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DBG("adc enter idle error,status = %d\n", status);
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return 1;
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}
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#endif
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ret = writeSpiDate(adc); //send test cmd
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if (ret < 0) {
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//DBG("cmd = %x\n", adc->cmd);
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return ret;
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}
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ret = readSpiDate(adc);
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if (ret < 0) {
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//DBG("result = %x\n", adc->result);
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return ret;
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}
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if (adc->result != ((adc->cmd >> 12) | 0x8000)) {
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DBG("cmd error\n");
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return CMD_ERR;
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}
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again:
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adc->cmd = CMD_GSC_ADC_NOP;
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ret = writeSpiDate(adc); //send nop cmd
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if (ret < 0) {
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DBG("send nop cmd error\n");
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return ret;
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}
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ret = readSpiDate(adc);
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if (ret < 0) {
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DBG("in read result = %x\n", adc->result);
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return ret;
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}
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if ((adc->result & 0xf000) == 0xf000)
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goto again;
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if ((adc->result & 0xf000) == 0) {
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adc->result &= 0x0fff;
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DBG("get result success, result = %d\n", adc->result);
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return adc->result;
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} else {
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DBG("get adc result error, result = %d\n", adc->result);
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return RESULT_ERR;
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}
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}
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static const struct adc_class_ops gsc3280_adc_ops = {
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.convert = gsc3280AdcCon,
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};
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static int adc_sysctl(struct gsc_adc_dev *adc)
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{
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int cnt = 0;
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writel(0x09, (volatile unsigned int *)0xbc04a034); //spi0 divid freq
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writel(0x01, adc->regs + GSC_SPI_SEABAUR); //spi_clik divid freq,4 divid freq
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writel(0x0f07, adc->regs + GSC_SPI_CTRL);
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msleep(300);
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writel(0x00, adc->regs + GSC_SPI_CS); //spi adc cs
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while(1) {
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writel(0x00, adc->regs + GSC_SPI_DA_S);
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while (readl(adc->regs + GSC_SPI_SR) & GSC_SPI_SR_BUSY) {
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;
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}
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if (readl(adc->regs + GSC_SPI_DA_S) == 0x8000) {
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DBG("spi0 stat OK!\n");
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return 0;
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}
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if (cnt++ > 10000) {
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DBG("cnt over, spi0 stat error!\n");
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return -1;
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}
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}
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}
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static int __devinit gsc3280_adc_probe(struct platform_device *pdev)
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{
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int ret = 0, size = 0;
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unsigned long rate = 0;
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struct gsc_adc_dev *adc;
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struct resource *mem, *ioarea;
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DBG("############\n");
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printk(KERN_INFO "GSC3280 spi0 adc probe start\n");
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adc = kzalloc(sizeof(struct gsc_adc_dev), GFP_KERNEL);
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if (adc == NULL) {
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DBG("failed to allocate adc_core_dev\n");
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return -ENOMEM;
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}
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!mem) {
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DBG("no mem resource.\n");
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ret = -EINVAL;
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goto err_alloc;
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}
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size = resource_size(mem);
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ioarea = request_mem_region(mem->start, size, pdev->name);
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if (!ioarea) {
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DBG("SPI region already claimed.\n");
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ret = -EBUSY;
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goto err_alloc;
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}
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adc->regs = ioremap_nocache(mem->start, resource_size(mem));
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if (!adc->regs) {
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DBG("SPI region already mapped.\n");
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ret = -ENOMEM;
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goto err_mem;
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}
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DBG("probe: mapped spi0 base=%p.\n", adc->regs);
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adc->clk = clk_get(NULL, "spi0");
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if (IS_ERR(adc->clk)) {
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DBG("failed to find watchdog clock source.\n");
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ret = PTR_ERR(adc->clk);
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goto err_map;
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}
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rate = clk_get_rate(adc->clk);
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DBG("rate is %ld.\n", rate);
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clk_enable(adc->clk);
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ret = adc_sysctl(adc);
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if (ret != 0)
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goto err_map;
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spin_lock_init(&adc->lock);
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INIT_LIST_HEAD(&adc->device_entry);
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strlcpy(adc->name, GSC3280_ADC_NAME, sizeof(adc->name));
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mutex_lock(&gsc3280_adc_list_lock);
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list_add(&adc->device_entry, &gsc3280_adc_list);
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mutex_unlock(&gsc3280_adc_list_lock);
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adc->adc_dev = adc_device_register(adc->name, &pdev->dev, &gsc3280_adc_ops, THIS_MODULE);
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if (IS_ERR(adc->adc_dev)) {
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ret = PTR_ERR(adc->adc_dev);
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DBG("unable to register the class device\n");
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goto err_clk;
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}
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platform_set_drvdata(pdev, adc);
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printk(KERN_INFO "GSC3280 adc probe SUCCESS.\n");
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DBG("############\n");
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return 0;
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err_clk:
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clk_disable(adc->clk);
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clk_put(adc->clk);
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err_map:
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iounmap(adc->regs);
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err_mem:
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release_mem_region(mem->start, size);
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mem = NULL;
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err_alloc:
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kfree(adc);
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printk(KERN_INFO "!!!!!!GSC3280 adc probe error!!!!!!\n");
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return ret;
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}
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static int __devexit gsc3280_adc_remove(struct platform_device *pdev)
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{
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struct gsc_adc_dev *adc = platform_get_drvdata(pdev);
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iounmap(adc->regs);
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clk_disable(adc->clk);
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clk_put(adc->clk);
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adc_device_unregister(adc->adc_dev);
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kfree(adc);
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return 0;
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}
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//#ifdef CONFIG_PM
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#if 0
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static int gsc3280_adc_suspend(struct platform_device *pdev, pm_message_t state)
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{
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struct adc_core_dev *adc = platform_get_drvdata(pdev);
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unsigned long flags;
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u32 con;
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spin_lock_irqsave(&adc->lock, flags);
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con = readl(adc->regs + S3C2410_ADCCON);
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con |= S3C2410_ADCCON_STDBM;
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writel(con, adc->regs + S3C2410_ADCCON);
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disable_irq(adc->irq);
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spin_unlock_irqrestore(&adc->lock, flags);
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clk_disable(adc->clk);
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return 0;
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}
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static int gsc3280_adc_resume(struct platform_device *pdev)
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{
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struct adc_core_dev *adc = platform_get_drvdata(pdev);
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clk_enable(adc->clk);
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enable_irq(adc->irq);
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writel(adc->prescale | S3C2410_ADCCON_PRSCEN,
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adc->regs + S3C2410_ADCCON);
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return 0;
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}
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#else
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#define gsc3280_adc_suspend NULL
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#define gsc3280_adc_resume NULL
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#endif
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static struct platform_driver gsc3280adc_driver = {
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.driver = {
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.name = "adc-core",
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.owner = THIS_MODULE,
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},
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.probe = gsc3280_adc_probe,
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.remove = __devexit_p(gsc3280_adc_remove),
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.suspend = gsc3280_adc_suspend,
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.resume = gsc3280_adc_resume,
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};
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static int __init gsc3280_adc_init(void)
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{
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int ret = 0;
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ret = platform_driver_register(&gsc3280adc_driver);
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if (ret != 0)
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DBG("!!!!!!gsc adc core register error!!!!!!\n");
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return ret;
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}
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static void __exit gsc3280_adc_exit(void)
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{
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platform_driver_unregister(&gsc3280adc_driver);
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}
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module_init(gsc3280_adc_init);
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module_exit(gsc3280_adc_exit);
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MODULE_AUTHOR("Davied<apple_guet@126.com>");
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MODULE_DESCRIPTION("gsc3280 spi0 adc Driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:gsc3280-spi0 adc");
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