92 lines
2.5 KiB
C
92 lines
2.5 KiB
C
/*
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* Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
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* Author: Fuxin Zhang, zhangfx@lemote.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/interrupt.h>
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#include <asm/irq_cpu.h>
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#include <asm/i8259.h>
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#include <loongson.h>
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//FIXME: Only provide functionality for hs3210, should be move to a new place lately.
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#include <soc_soc.h>
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#include <soc_soc_int.h>
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struct soc_soc_intc_regs volatile *soc_soc_hw0_icregs
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= (struct soc_soc_intc_regs volatile *)(KSEG1ADDR(SOC_SOC_INTC_BASE));
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static struct irqaction cascade_irqaction = {
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.handler = no_action,
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.name = "cascade",
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};
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void hs3210_soc_irq_init(int irq_base);
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void __init mach_init_irq(void)
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{
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/* init all controller
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* 16-23 ------> mips cpu interrupts
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* 24-46 ------> hs3210 soc interrupts
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*/
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clear_c0_status(ST0_IM | ST0_BEV);
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#if 0
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local_irq_disable();
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/* active level setting */
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/* uart, keyboard, and mouse are active high */
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soc_soc_hw0_icregs->int_pol = ~( (INT_PCI_INTA)|(INT_PCI_INTB)|(INT_PCI_INTC)|(INT_PCI_INTD));//pci active low
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/* make all interrupts level triggered */
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soc_soc_hw0_icregs->int_edge = 0x00000000;
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/* mask all interrupts */
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soc_soc_hw0_icregs->int_clr = 0xffffffff;
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// soc_soc_hw0_icregs->int_en = 0x00000000;
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/* make all interrupts steer to cpu int0 */
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/* In fact interrupts can pass to cpu int1*/
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soc_soc_hw0_icregs->int_steer = 0x00000000;
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/* enable uart0 and mac0 in hsb interrupt controller */
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soc_soc_hw0_icregs->int_en = 0x802;
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// *(char *)0xbf004081 = 0x1;
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#endif
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mips_cpu_irq_init();
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hs3210_soc_irq_init(MIPS_CPU_IRQ_BASE + 8);
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setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction);
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/* 8259 irq at IP7 */
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setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction);
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}
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void soc_soc_hw0_irqdispatch(void);
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char uart_iir_tmp;
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asmlinkage void mach_irq_dispatch(unsigned int pending)
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{
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if (pending & CAUSEF_IP7) {
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do_IRQ(23);
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/* add for uart interrupt polling */
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uart_iir_tmp = *(volatile unsigned char*)(0xbc108000 + 0x2);
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if((uart_iir_tmp)){
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int irq = MIPS_CPU_IRQ_BASE + 8;
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irq += SOC_SOC_UART0_IRQ;
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do_IRQ(irq);
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}
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/* add end */
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} else if (pending & CAUSEF_IP2) {
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soc_soc_hw0_irqdispatch();
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} else {
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// printk("spurious: cause = 0x%x, status = 0x%x\n", cause, status);
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spurious_interrupt();
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}
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}
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