/*
 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
 * Author: Fuxin Zhang, zhangfx@lemote.com
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 */
#include <linux/interrupt.h>

#include <asm/irq_cpu.h>
#include <asm/i8259.h>

#include <loongson.h>

//FIXME: Only provide functionality for hs3210, should be move to a new place lately.
#include <soc_soc.h>
#include <soc_soc_int.h>

struct soc_soc_intc_regs volatile *soc_soc_hw0_icregs
	= (struct soc_soc_intc_regs volatile *)(KSEG1ADDR(SOC_SOC_INTC_BASE));

static struct irqaction cascade_irqaction = {
	.handler = no_action,
	.name = "cascade",
};

void hs3210_soc_irq_init(int irq_base);
void __init mach_init_irq(void)
{
	/* init all controller
	 *   16-23         ------> mips cpu interrupts
	 *   24-46        ------> hs3210 soc interrupts
	 */

	clear_c0_status(ST0_IM | ST0_BEV);
#if 0
	local_irq_disable();

	/* active level setting */
	/* uart, keyboard, and mouse are active high */
	soc_soc_hw0_icregs->int_pol = ~( (INT_PCI_INTA)|(INT_PCI_INTB)|(INT_PCI_INTC)|(INT_PCI_INTD));//pci active low

	/* make all interrupts level triggered */ 
	soc_soc_hw0_icregs->int_edge = 0x00000000;
	
	/* mask all interrupts */
	soc_soc_hw0_icregs->int_clr = 0xffffffff;
   //	soc_soc_hw0_icregs->int_en = 0x00000000;
	
	/* make all interrupts steer to cpu int0 */
	/* In fact interrupts can pass to cpu int1*/
	soc_soc_hw0_icregs->int_steer = 0x00000000;

	/* enable uart0 and mac0 in hsb interrupt controller */
	soc_soc_hw0_icregs->int_en = 0x802;

//	*(char *)0xbf004081 = 0x1;
#endif
	mips_cpu_irq_init();
	hs3210_soc_irq_init(MIPS_CPU_IRQ_BASE + 8);

	setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction);
	/* 8259 irq at IP7 */
	setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction);
}

void soc_soc_hw0_irqdispatch(void);
char uart_iir_tmp;
asmlinkage void mach_irq_dispatch(unsigned int pending)
{
	if (pending & CAUSEF_IP7) {
		do_IRQ(23);

		/* add for uart interrupt polling */
		uart_iir_tmp = *(volatile unsigned char*)(0xbc108000 + 0x2);
		if((uart_iir_tmp)){
			int irq = MIPS_CPU_IRQ_BASE + 8;
			irq += SOC_SOC_UART0_IRQ;
			do_IRQ(irq);
		}

		/* add end */
	}  else if (pending & CAUSEF_IP2) {
		soc_soc_hw0_irqdispatch();
	} else {
		// printk("spurious: cause = 0x%x, status = 0x%x\n", cause, status);
		spurious_interrupt();
	}
}