83 lines
2.3 KiB
C
83 lines
2.3 KiB
C
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/*
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* Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
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* Author: Fuxin Zhang, zhangfx@lemote.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/interrupt.h>
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#include <asm/irq_cpu.h>
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//#include <asm/i8259.h>
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#include <loongson.h>
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//FIXME: Only provide functionality for gsc3280, should be move to a new place lately.
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#include <gsc3280/gsc3280_int.h>
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//struct soc_soc_intc_regs volatile *soc_soc_hw0_icregs
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// = (struct soc_soc_intc_regs volatile *)(KSEG1ADDR(SOC_SOC_INTC_BASE));
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static struct irqaction cascade_irqaction = {
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.handler = no_action,
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.name = "cascade",
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};
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static irqreturn_t blx_buserror_action(int irq, void *dev_id)
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{
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// struct pt_regs *regs = get_irq_regs();
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volatile unsigned long int *buserror_status = (unsigned long int *)0xbc04a0c4;
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*buserror_status = 0x1;
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//BusError not accurately, so printk is useless.
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#if 0
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printk(KERN_ERR "%s BusError, EPC: %lx RA: %lx\n",
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(regs->cp0_cause & 4) ? "Data" : "Instruction",
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regs->cp0_epc,
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regs->regs[31]);
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#endif
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return IRQ_HANDLED;
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}
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static struct irqaction buserror_irqaction = {
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.handler = blx_buserror_action,
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.name = "BusError",
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};
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void gsc3280_soc_irq_init(int irq_base);
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void __init mach_init_irq(void)
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{
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/* init all controller
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* 16-23 ------> mips cpu interrupts
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* 24-46 ------> gsc3280 soc interrupts
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*/
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clear_c0_status(ST0_IM | ST0_BEV);
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local_irq_disable();
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mips_cpu_irq_init();
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gsc3280_soc_irq_init(MIPS_CPU_IRQ_BASE + 8);
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setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction);
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/* 8259 irq at IP7 */
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setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction);
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/* response buserror from DWC interrupt, IRQ number in dwc-irq.c */
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setup_irq(MIPS_CPU_IRQ_BASE + 8 + 30, &buserror_irqaction);
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}
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void soc_soc_hw0_irqdispatch(void);
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asmlinkage void mach_irq_dispatch(unsigned int pending)
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{
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if (pending & CAUSEF_IP7) {
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do_IRQ(MIPS_CPU_IRQ_BASE + 7);
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/* add end */
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} else if (pending & CAUSEF_IP2) {
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soc_soc_hw0_irqdispatch();
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} else {
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// printk("spurious: cause = 0x%x, status = 0x%x\n", cause, status);
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spurious_interrupt();
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}
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}
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