142 lines
4.8 KiB
C
142 lines
4.8 KiB
C
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/*
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*
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* BRIEF MODULE DESCRIPTION
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* GC SOC system controller defines.
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*
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* Copyright 2000 MontaVista Software Inc.
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* Author: GC.
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* huoweiming@gmail.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __SOC_SOC__H__
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#define __SOC_SOC__H__
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#include <asm/addrspace.h>
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/* SOC SOC Memory control regs */
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#define SOC_SOC_SD_BASE 0x1f000000
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#define REG_SD_TIMING 0x0
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#define REG_SD_MOD_SIZE 0x4
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/* LCD regs */
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#define SOC_SOC_LCD_BASE 0x1f001000
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#define REG_LCD_CTRL 0x00
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#define REG_LCD_STAT 0x04
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#define REG_LCD_HTIM 0x08
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#define REG_LCD_VTIM 0x0c
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#define REG_LCD_HVLEN 0x10
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#define REG_LCD_VBARa 0x14
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#define REG_LCD_VBARb 0x18
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#define REG_LCD_C0XY 0x30
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#define REG_LCD_C0BAR 0x34
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#define REG_LCD_C0CR 0x40
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#define REG_LCD_C1XY 0x70
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#define REG_LCD_C1BAR 0x74
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#define REG_LCD_CICR 0x80
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#define REG_LCD_PCLT 0x800
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#define BIT_MAC_MIICMD_WCTRLDATA 0x00000004 // Write Control Data
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/* MAC regs */
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#define REG_MAC_MODER 0x00000000 // 0x00
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#define REG_MAC_INT_SOURCE 0x00000004 // 0x04
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#define REG_MAC_INT_MASK 0x00000008 // 0x08
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#define REG_MAC_IPGT 0x0000000C // 0x0C
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#define REG_MAC_IPGR1 0x00000010 // 0x10
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#define REG_MAC_IPGR2 0x00000014 // 0x14
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#define REG_MAC_PACKETLEN 0x00000018 // 0x18
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#define REG_MAC_COLLCONF 0x0000001C // 0x1C
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#define REG_MAC_TX_BD_NUM 0x00000020 // 0x20
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#define REG_MAC_CTRLMODER 0x00000024 // 0x24
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#define REG_MAC_MIIMODER 0x00000028 // 0x28
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#define REG_MAC_MIICOMMAND 0x0000002C // 0x2C
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#define REG_MAC_MIIADDRESS 0x00000030 // 0x30
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#define REG_MAC_MIITX_DATA 0x00000034 // 0x34
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#define REG_MAC_MIIRX_DATA 0x00000038 // 0x38
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#define REG_MAC_MIISTATUS 0x0000003C // 0x3C
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#define REG_MAC_ADDR0 0x00000040 // 0x40
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#define REG_MAC_ADDR1 0x00000044 // 0x44
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#define REG_MAC_HASH0 0x00000048 // 0x48
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#define REG_MAC_HASH1 0x0000004C // 0x4C
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#define REG_MAC_TX_CTRL 0x00000050 // 0x50
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#define REG_MAC_BD_BASE 0x00000400 // 0x400
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/* AHB BUS control regs */
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#define SOC_SOC_AHB_MISC_BASE 0x1f003200
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#define AHB_MISC_CTRL 0x00
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//#define AHB_CLK 33333333
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#define AHB_CLK 50000000
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/* Interrupt register */
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#define REG_INT_EDGE 0x04
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#define REG_INT_STEER 0x08
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#define REG_INT_POL 0x0c
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#define REG_INT_SET 0x10
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#define REG_INT_CLR 0x14
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#define REG_INT_EN 0x18
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#define REG_INT_ISR 0x1c
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#define SOC_SOC_INTC_BASE SOC_SOC_AHB_MISC_BASE + REG_INT_EDGE
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/* GPIO register */
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#define REG_GPIO_OE_AHB 0x20
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#define REG_GPIO_R_AHB 0x24
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#define REG_GPIO_W_AHB 0x28
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/* SPI regs */
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#define SOC_SOC_SPI_BASE 0x1f004000
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#define REG_SPCR 0x00
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#define REG_SPSR 0x01
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#define REG_SPDR 0x02
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#define REG_SPER 0x03
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/* UART regs */
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#define SOC_SOC_MAC1_BASE 0x1f005200
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#define SOC_SOC_MAC2_BASE 0x1f005300
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#define SOC_SOC_UART0_BASE 0x1f004080
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#define SOC_SOC_UART1_BASE 0x1f004090
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/* PS2 regs */
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#define SOC_PS2_BASE 0x1f004040
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#define PS2_RIBUF 0x00 /* Read */
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#define PS2_WOBUF 0x00 /* Write */
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#define PS2_RSR 0x04 /* Read */
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#define PS2_WSC 0x04 /* Write */
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#define PS2_DLL 0x08
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#define PS2_DLH 0x09
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/* APB BUS control regs */
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#define SOC_SOC_APB_MISC_BASE 0x1f004100
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#define REG_GPIO_OE_APB 0x00
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#define REG_GPIO_R_APB 0x10
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#define REG_GPIO_W_APB 0x20
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#define REG_APB_MISC_CTL 0x40
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#define APB_CLK AHB_CLK
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//AC97
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#define SOC_AC97_REGS_BASE 0x1f004200
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//PCI
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#define SOC_SOC_PCI_REGS_BASE 0x1f002000
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#endif
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