44 lines
1.5 KiB
Plaintext
44 lines
1.5 KiB
Plaintext
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* Freescale MSI interrupt controller
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Required properties:
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- compatible : compatible list, contains 2 entries,
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first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
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etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
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the parent type.
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- reg : should contain the address and the length of the shared message
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interrupt register set.
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- msi-available-ranges: use <start count> style section to define which
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msi interrupt can be used in the 256 msi interrupts. This property is
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optional, without this, all the 256 MSI interrupts can be used.
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Each available range must begin and end on a multiple of 32 (i.e.
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no splitting an individual MSI register or the associated PIC interrupt).
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- interrupts : each one of the interrupts here is one entry per 32 MSIs,
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and routed to the host interrupt controller. the interrupts should
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be set as edge sensitive. If msi-available-ranges is present, only
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the interrupts that correspond to available ranges shall be present.
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- interrupt-parent: the phandle for the interrupt controller
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that services interrupts for this device. for 83xx cpu, the interrupts
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are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
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to MPIC.
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Example:
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msi@41600 {
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compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
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reg = <0x41600 0x80>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xe0 0
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0xe1 0
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0xe2 0
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0xe3 0
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0xe4 0
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0xe5 0
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0xe6 0
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0xe7 0>;
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interrupt-parent = <&mpic>;
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};
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